LCK4994

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute
stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.

The LCK4993 and LCK4994 low-voltage PLL clock drivers offer user-selectable control over system clock functions.The multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems.

LCK4994 terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews at LVTTL levels. The outputs are arranged in five banks. Banks 1-4 allow a divide function of 1 to 12, while simultaneously allowing phase adjustments in 625 ps-1300 ps increments up to 10.4 ns. One of the output banks also includes an independent clock invert function. The feedback bank consists of two outputs that allow divide-by functionality from 1 to 12 and limited phase adjustments. Any one of these eighteen outputs can be connected to the feedback input or drive other inputs.

Selectable reference input is a fault tolerance feature that allows smooth change over to the secondary clock source when the primary clock source is not in operation. The reference inputs and feedback inputs are configurable to accommodate both LVTTL or differential (LVPECL) inputs. The completely integrated PLL reduces jitter and simplifies board layout.