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Part Number: LP61L1024
Description: The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits...
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LP61L1024
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DataSheet
General Description
LP61L1024 General Description
The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply.
Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing.
Data retention is guaranteed at a power supply voltage as low as 2.0V.
LP61L1024 Maximum Ratings
VCC to GND .............................................. -0.5V to +7.0V
IN, IN/OUT Volt to GND .....................-0.5V to VCC +0.5V
Operating Temperature, Topr ...................... 0 to +70
Storage Temperature, Tstg..................... -55 to +125
Temperature Under Bias, Tbias................ -10 to +85
Power Dissipation, Pt................................................1.0W
Soldering Temp. & Time .............................260°C, 10 sec
IN, IN/OUT Volt to GND .....................-0.5V to VCC +0.5V
Operating Temperature, Topr ...................... 0 to +70
Storage Temperature, Tstg..................... -55 to +125
Temperature Under Bias, Tbias................ -10 to +85
Power Dissipation, Pt................................................1.0W
Soldering Temp. & Time .............................260°C, 10 sec
LP61L1024 Features
· Single +3.3V power supply
· Access times: 12/15 ns (max.)
· Current: Operating: 170mA (max.) Standby: 10mA (max.)
· Full static operation, no clock or refreshing required
·All inputs and outputs are directly TTL compatible
· Common I/O using three-state output
· Output enable and two chip enable inputs for easy application
· Data retention voltage: 2.0V (min.)
· Available in 32-pin SOJ 300 mil, 32-pin TSOP and 32- pin TSSOP and 36-pin CSP packages
· Access times: 12/15 ns (max.)
· Current: Operating: 170mA (max.) Standby: 10mA (max.)
· Full static operation, no clock or refreshing required
·All inputs and outputs are directly TTL compatible
· Common I/O using three-state output
· Output enable and two chip enable inputs for easy application
· Data retention voltage: 2.0V (min.)
· Available in 32-pin SOJ 300 mil, 32-pin TSOP and 32- pin TSSOP and 36-pin CSP packages
LP61L1024 Connection Diagram
LP61L1024
PDF/DataSheet Download
- Datasheet: LP61L1024
- File Size: 183177 KB
- Manufacturer: AMICC [AMIC Technology]
- Click here to Download
- ·LP61L1008
- AMICC [AMIC Technology]
- 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
- 146316 KB
- ·LP61L1008A
- AMICC [AMIC Technology]
- 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
- 121194 KB
- ·LP61L1008AS-10
- AMICC [AMIC Technology]
- 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
- 121194 KB
- ·LP61L1008AS-12
- AMICC [AMIC Technology]
- 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
- 121194 KB
- ·LP61L1008AS-8
- AMICC [AMIC Technology]
- 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
- 121194 KB
- ·LP61L1008S-12
- AMICC [AMIC Technology]
- 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
- 146316 KB
- ·LP61L1008S-15
- AMICC [AMIC Technology]
- 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
- 146316 KB
- ·LP61L1008X-12
- AMICC [AMIC Technology]
- 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
- 146316 KB
LP61L1024 Relative Products
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The LP61L1008A is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply.Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus...
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The LP61L1008 is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply.Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus ...
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