LP61L1024

Features:

 · Single +3.3V power supply
 · Access times: 12/15 ns (max.)
 · Current: Operating: 170mA (max.) Standby: 10mA (max.)
 · Full static operation, no clock or refreshing required
 ·All inputs and outputs are directly TTL compatible
 · Common I/O using three-state output
 · Output enable and two chip enable inputs for easy application
 · Data retention voltage: 2.0V (min.)
 · Available in 32-pin SOJ 300 mil, 32-pin TSOP and 32- pin TSSOP and 36-pin CSP packages


Pinout




Specifications

VCC to GND .............................................. -0.5V to +7.0V
IN, IN/OUT Volt to GND .....................-0.5V to VCC +0.5V
Operating Temperature, Topr ...................... 0  to +70
Storage Temperature, Tstg..................... -55  to +125
Temperature Under Bias, Tbias................ -10  to +85
Power Dissipation, Pt................................................1.0W
Soldering Temp. & Time .............................260°C, 10 sec


Description

The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply.

Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.

Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing.

Data retention is guaranteed at a power supply voltage as low as 2.0V.