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LRS1341

Features: • Flash Memory and SRAM• Stacked Die Chip Scale Package• 72-ball CSP (FBGA072-P-0811) plastic package• Power supply: 2.7 V to 3.6 V• Operating temperature: -25°C to +85°C• Flash Memory Access time (MAX.): 100 ns Operating current (MAX.):The current for...

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SeekIC No. : 004399497 Detail

LRS1341: Features: • Flash Memory and SRAM• Stacked Die Chip Scale Package• 72-ball CSP (FBGA072-P-0811) plastic package• Power supply: 2.7 V to 3.6 V• Operating temperature: -2...

LRS1341 Data Sheet

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Part Number:
LRS1341
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Flash Memory and SRAM
• Stacked Die Chip Scale Package
• 72-ball CSP (FBGA072-P-0811) plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
Access time (MAX.): 100 ns
Operating current (MAX.):
The current for F-VCC pin
Read: 25 mA (tCYCLE = 200 ns)
Word write: 17 mA
Block erase: 17 mA
Deep power down current (the current for
F-VCC pin): 10 A (MAX. F-CE F-VCC - 0.2 V,
F-RP -0.2 V, F-VPP 0.2 V)
Optimized array blocking architecture
Two 4K-word boot blocks
Six 4K-word parameter blocks
Thirty-one 32K-word main blocks
Top/Bottom boot location versions
Extended cycling capability
100,000 block erase cycles
Enhanced automated suspend options
Word write suspend to read
Block erase suspend to word write
Block erase suspend to read
• SRAM
Access time (MAX.): 85 ns
Operating current (MAX.):
45 mA
8 mA (tRC, tWC = 1 s)
Standby current: 45 A (MAX.)
Data retention current: 35 A (MAX.)


Specifications

PARAMETER

SYMBOL

RATINGS

UNIT

NOTES

Supply voltage

VCC

-0.2 to +3.9

V

1, 2

Input voltage

VIN

-0.2 to VCC +0.3

V

1, 3, 4

Operating temperature

TOPR

-25 to +85

 

Storage temperature

TSTG

-55 to +125

 

F-VPP voltage

F-VPP

-0.2 to +14.0

V

1, 4, 5

F-RP voltage

F-RP

-0.5 to +14.0

V

1, 4, 5

NOTES:
1. The maximum applicable voltage on any pins with respect to GND.
2. Except F-VPP.
3. Except F-RP.
4. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
5. +14.0 V overshoot is allowed when the pulse width is less than 20 ns.


Description

The LRS1341/LRS1342 is a combination memory organized as 1,048,576 × 16-bit flash memory and 131,072 × 16-bit static RAM in one package.


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