LS96

The LS96 is a 5-bit shift register with both No serial and parallel (ones transfer) data For entry. Since the *96 has the output of each stage available as well as a D-type serial input and ones transfer inputs on IN each stage, it can be used in 5-bit serial-to-parallel, serial-to-serial and some parallel-to-serial data operations. The LS96 is five master/slave flip-flops connected to perform right shift. The flip-flops change state on the LOW-to-HIGH No transition of the clock. The Serial A7 input is edge-triggered and must be stable only one set-up time before the LOW-to-HIGH clock transition. Each flip-flop has asynchronous set inputs, allowing them to be independently set HIGH. The set inputs are controlled by a common active HIGH Preset Enable (PE) input. The PE input is not buffered, and care must be taken not to overload the driving element. When the PE is HIGH, a HIGH on the Preset inputs will set the associated flip-flope HIGH. A LOW on the A-E inputs will cause "no change" in the appropriate flip-flops. The asynchronous active LOW Clear (MR) is buffered. When LOW, the MR overrides the clock and clears the regl ter if the PE is not active. The Preset Inputs override the MR, forcing the fllp-tlops HIGH if both are activated simultaneously. However, for predictable operation, both signals should not be deactivated simultaneously.

The features of LS96 can be summarized as (1)5-bit parallel-to-serial or serial-to-parallel converter; (2)asynchronous ones transfer preset entry; (3)buttered positive-triggered clock; (4)buffered actlve low clear (master reset).

The absolute maximum ratings of LS96 are (1)VCC supply voltage: 7.0V; (2)VIN input voltage: -0.5 to +7.0V; (3)IIN input current: -30 to +5mA; (4)VOUT voltage applied to output in high output state: -0.5 to +VCC; (5)TA operating free-air temperature range: 0 to 70°C.