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Part Number: M368L3223DTL
Description: The Samsung M368L3223DTL is 32M bit x 64 Double Data Rate SDRAM high density memory modules. The Samsu...
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M368L3223DTL
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DataSheet
General Description
M368L3223DTL General Description
The Samsung M368L3223DTL is 32M bit x 64 Double Data Rate SDRAM high density memory modules. The Samsung M368L3223DTL consists of eight CMOS 32M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages mounted on a 184pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The M368L3223DTL is Dual In-line Memory Modules and inten-ded for mounting into 184pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
M368L3223DTL Maximum Ratings
| Parameter |
Symbol |
Value |
Unit |
| Voltage on any pin relative to Vss |
VIN, VOUT |
-0.5 ~ 3.6 |
V |
| Voltage on VDD supply relative to Vss |
VDD |
-1.0 ~ 3.6 |
V |
| Voltage on VDDQ supply relative to Vss |
VDDQ |
-1.0 ~ 3.6 |
V |
| Storage temperature |
TSTG |
-55 ~ +150 |
|
| Power dissipation |
PD |
12 |
W |
| Short circuit current |
IOS |
50 |
mA |
Note :Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
M368L3223DTL Features
• Performance range
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1250 mil, double sided component
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1250 mil, double sided component
M368L3223DTL
PDF/DataSheet Download
- Datasheet: M368L3223DTL
- File Size: 84384 KB
- Manufacturer: SAMSUNG [Samsung semiconductor]
- Click here to Download
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