M36W108AT

The M36W108A is multi-chip device containing an 8 Mbit boot block Flash memory and a 1 Mbit of SRAM. The device is offered in the new Chip Scale Package solutions: LBGA48 1.0mm ball pitch and LGA48 1.0mm land pitch.
The two components, of the package's overall 9 Mbit of memory, are distinguishable by use of the three chip enable lines: EF for the Flash memory, E1S and E2S for the SRAM.
The Flash memory component is identical with the M29W008A device. It is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by- Byte basis using only a single 2.7V to 3.6V VCCF supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks.
Instructions for Read/Reset, Auto Select for reading the Electronic Signature, Programming, Block and Chip Erase, Erase Suspend and Resume are written to the device in cycles of commands to a Command Interface using standard microprocessor write timings. The SRAM component is a low power SRAM that features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7V to 3.6V V_CCS supply, and all inputs and outputs are TTL compatible.