Purchase M378T3354BG(Z)0-CD5, In-stock M378T3354BG(Z)0-CD5 From SeekIC.
- Table of contents:
M378T3354BG(Z)0-CD5
-
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DataSheet
General Description
M378T3354BG(Z)0-CD5 Maximum Ratings
|
Symbol |
Parameter |
Rating |
Units |
Notes |
|
VDD |
Voltage on VDD pin relative to VSS |
- 1.0 V ~ 2.3 V |
V |
1 |
|
VDDQ |
Voltage on VDDQ supply relative to Vss |
- 0.5 V ~ 2.3 V |
V |
1 |
|
VDDL |
Voltage on VDDL pin relative to VSS |
- 0.5 V ~ 2.3 V |
V |
1 |
|
VIN, VOUT |
VOUT Voltage on any pin relative to VSS |
- 0.5 V ~ 2.3 V |
V |
1 |
|
TSTG |
Storage Temperature |
-55 to +100 |
|
1,2 |
Note :
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
M378T3354BG(Z)0-CD5 Features
• Performance range
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refresh Period 7.8us at lower than a TCASE 85 , 3.9us at 85 < TCASE 95
- support High Temperature Self-Refresh rate enable feature
• Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16
• All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung's Device operation & Timing diagram.
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refresh Period 7.8us at lower than a TCASE 85 , 3.9us at 85 < TCASE 95
- support High Temperature Self-Refresh rate enable feature
• Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16
• All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung's Device operation & Timing diagram.
M378T3354BG(Z)0-CD5/CC
PDF/DataSheet Download
- Datasheet: M378T3354BG(Z)0-CD5/CC
- File Size: 477947 KB
- Manufacturer: SAMSUNG [Samsung semiconductor]
- Click here to Download
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