M48Z512A

With valid V_CC applied, the M48Z512A/Y/V operates as a conventional BYTEWIDE^TM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself t_WP after V_CC falls below V_PFD. All outputs become high impedance, and all inputs are treated as "don't care."

If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time t_WP, write protection takes place. When V_CC drops below V_SO, the control circuit switches power to the internal energy source which preserves data.

The internal coin cell will maintain data in the M48Z512A/Y/V after the initial application of V_CC for an accumulated period of at least 10 years when V_CC is less than V_SO. As system power returns and V_CC rises above V_SO, the battery is disconnected, and the power supply is switched to external V_CC. Write protection continues for t_ER after V_CC reaches V_PFD to allow for processor stabilization. After t_ER, normal RAM operation can resume.

For more information on Battery Storage Life refer to the Application Note AN1012.