M50FLW040A

`FLASH MEMORY
Compatible with either the LPC interface or the FWH interface (Intel Spec rev1.1) used in PC BIOS applications
5 Signal Communication Interface supporting Read and Write Operations
5 Additional General Purpose Inputs for platform design flexibility
Synchronized with 33MHz PCI clock
`8 BLOCKS OF 64 KBYTES
5 blocks of 64 KBytes each
3 blocks, subdivided into 16 uniform sectors of 4 KBytes each Two blocks at the top and one at the bottom (M50FLW040A) One block at the top and two at the bottom (M50FLW040B)
`ENHANCED SECURITY
Hardware Write Protect Pins for Block Protection
Register-based Read and Write Protection
`SUPPLY VOLTAGE
V_CC = 3 to 3.6V for Program, Erase and Read Operations
V_PP = 12V for Fast Program and Erase
`TWO INTERFACES
Auto Detection of Firmware Hub (FWH) or Low Pin Count (LPC) Memory Cycles for Embedded Operation with PC Chipsets
Address/Address Multiplexed (A/A Mux) Interface for programming equipment compatibility.
`PROGRAMMING TIME: 10s typical
`PROGRAM/ERASE CONTROLLER
Embedded Program and Erase algorithms
Status Register Bits
`PROGRAM/ERASE SUSPEND
Read other Blocks/Sectors during Program Suspend
Program other Blocks/Sectors during Erase Suspend
`ELECTRONIC SIGNATURE
Manufacturer Code: 20h
Device Code (M50FLW040A): 08h
Device Code (M50FLW040B): 28h

The M50FLW040 is a 4 Mbit (512Kb x8) non-volatile memory that can be read, erased and reprogrammed.These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines, an optional 12V power supply can be used to reduce the erasing and programming time.

The M50FLW040 memory is divided into 8 Uniform Blocks of 64 KBytes each, three of which are divided into 16 uniform sectors of 4 KBytes each (see APPENDIX A. for details). All blocks and sectors can be erased independently. So, it is possible to preserve valid data while old data is erased. Blocks can be protected individually to prevent accidental program or erase commands from modifying their contents.

Program and erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller M50FLW040 simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set to control the memory is consistent with the JEDEC standards.
Two different bus interfaces are supported by the memory:
` The primary interface, the FWH/LPC Interface, uses Intel's proprietary Firmware Hub (FWH) and Low Pin Count (LPC) protocol. This has been designed to remove the need for the ISA bus in current PC Chipsets. The M50FLW040 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets.
` The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers, for production line programming prior to fitting the device in a PC Motherboard.
The memory is supplied with all the bits erased (set to '1').