M54HC112

Features:

.HIGH SPEED
f_MAX = 67 MHz (TYP.) AT V_CC = 5 V
.LOWPOWER DISSIPATION
I_CC = 2 mA AT T_A = 25 °C
.HIGH NOISE IMMUNITY
V_NIH= V_NIL= 28% V_CC (MIN.)
.OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.SYMMETRICAL OUTPUT IMPEDANCE
|I_OH| = I_OL = 4 mA (MIN.)
.BALANCEDPROPAGATION DELAYS
t_PLH = t_PHL
.WIDE OPERATING VOLTAGE RANGE
V_CC (OPR) = 2 V TO 6 V
.PIN AND FUNCTION COMPATIBLE WITH 54/74LS112


Pinout




Specifications

Symbol	Parameter	Value	Unit
VCC	Supply Voltage	-0.5 to +7	V
VI	DC Input Voltage	-0.5 to VCC + 0.5	V
VO	DC Output Voltage	-0.5 to VCC + 0.5	V
IIK	DC Input Diode Current	± 20	mA
IOK	DC Output Diode Current	± 20	mA
IO	DC Output Source Sink Current Per Output Pin	± 25	mA
ICC or IGND	DC VCC or Ground Current	± 50	mA
PD	Power Dissipation	500 (*)	mW
Tstg	Storage Temperature	-65 to +150	oC
TL	Lead Temperature (10 sec)	300	oC

Description

   The M54/74HC112 is a high speed CMOS DUAL J-K FLIP-FLOPWITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The M54HC112/M74HC112 dual JK flip-flop features individual J,K, clock,andasynchronous setand clear inputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is high and the bistable will function as shown in the truth table. Input data is transferred to the input on the negative going edge of the clock pulse. All inputs are equipped withprotection circuitsagainst static discharge and transient excess voltage.