M66852J

M66850/851/852/853 are very high-speed and clock synchronous FIFO(First-In,First-Out) memories fabricated by high-speed CMOS technology.

These FIFOs are applicable for a data buffer as networks and communications.

The write operation is controlled by a write clock pin(WCLK) and two write enable pins(WEN1WEN2 ).

Data present at the data input pins(D0-D8) is written into the Synchronous FIFO on every rising write clock edge when the device is enabled for writing.

The read operation is controlled by a read clock pin(RCLK) and two read enable pins(REN1,REN2).

Data is read from the Synchronous FIFO on every rising read clock edge when the device is enabled for reading. An output enable pin(OE) controls the states of the data output pins(Q0-Q8).

MITSUBISHI FIFOs have four flags (EF,FF,PAE,PAF). The empty flag EF and the full flag FF are fixed flags. The almost empty flag PAE and the almost full flag PAF are programmable flags. The programmable flag offset is initiated by the load pin(LD).