M672061

The M672061F implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word size and depth with no timing penalties. Twin address pointers automatically generate internal read and write addresses, and no external address information are required for the Atmel FIFOs. Address pointers are automatically incremented with the write pin and read pin. The 9 bits wide data are used in data communications applications where a parity bit for error checking is necessary. The Retransmit pin resets the Read pointer to zero without affecting the write pointer. This is very useful for retransmitting data when an error is detected in the system.

Using an array of eight transistors (8T) memory cell, the M672061F combines an extremely low standby supply current (typ = 0.1 A) with a fast access time at 15 ns over the full temperature range. All versions offer battery backup data retention capability with a typical power consumption at less than 2 W.

For military/space applications that demand superior levels of performance and reliability the M672061F is processed according to the methods of the latest revision of the MIL PRF 38535 (Q and V) or ESA SCC 9000.