M95256

Features: Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) Single Supply Voltage: 4.5 to 5.5V for M95xxx 2.5 to 5.5V for M95xxx-W 1.8 to 5.5V for M95xxx-R High Speed 10MHz Clock Rate, 5ms Write Time Status Register Hardware Protection of the Status Register BYTE and PAGE W...

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M95256 Picture
SeekIC No. : 004407382 Detail

M95256: Features: Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) Single Supply Voltage: 4.5 to 5.5V for M95xxx 2.5 to 5.5V for M95xxx-W 1.8 to 5.5V for M95xxx-R High Speed 10MHz C...

floor Price/Ceiling Price

Part Number:
M95256
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/27

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Product Details

Description



Features:

Compatible with SPI Bus Serial Interface
    (Positive Clock SPI Modes)
Single Supply Voltage:
    4.5 to 5.5V for M95xxx
    2.5 to 5.5V for M95xxx-W
    1.8 to 5.5V for M95xxx-R
High Speed
    10MHz Clock Rate, 5ms Write Time
Status Register
Hardware Protection of the Status Register
BYTE and PAGE WRITE (up to 64 Bytes)
Self-Timed Programming Cycle
Adjustable Size Read-Only EEPROM Area
Enhanced ESD Protection
More than 100000 Erase/Write Cycles
More than 40-Year Data Retention



Pinout

  Connection Diagram


Specifications

Symbol
Parameter
Min.
Max.
Unit
TSTG
Storage Temperature
65
150
°C
TLEAD
Lead Temperature during Soldering
See note 1
°C
VO
Output Voltage
0.50
VCC+0.6
V
VI
Input Voltage
0.50
6.5
V
VCC
Supply Voltage
0.50
6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model) 2
4000
4000
V

 

Note:
1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)




Description

These electrically erasable programmable memory (EEPROM) devices are accessed by a high speed SPI-compatible bus. The memory array is
organized as 32768 x 8 bit (M95256) and 16384 x 8 bit (M95128).

The M95256 is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 2. and Figure 2..
The device is selected when Chip Select (S) is taken Low. Communications with the device can be interrupted using Hold HOLD).


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