Purchase MBM29LV160TM/BM 90, In-stock MBM29LV160TM/BM 90 From SeekIC.
Part Number: MBM29LV160TM/BM 90
Description: The MBM29LV160TM/BM is a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes by 8 bits or 2M words ...
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MBM29LV160TM/BM 90
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DataSheet
General Description
MBM29LV160TM/BM 90 General Description
The MBM29LV160TM/BM is a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes by 8 bits or 2M words by 16 bits. The MBM29LV160TM/BM is offered in 48-pin TSOP(1) and 48-ball FBGA. The device is designed to be programmed in-system with the standard 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for program or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
The standard MBM29LV160TM/BM offers access times of 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls.
MBM29LV160TM/BM 90 Maximum Ratings
| Parameter |
Conditions |
Rating |
Units | |
|
Min |
Max | |||
| Storage Temperature |
Tstg |
55 |
+125 |
°C |
| Ambient Temperature with Power Applied |
TA |
40 |
+70 |
°C |
| Voltage with Respect to Ground All Pins except A9, OE, RESET *1, *2 |
VIN, VOUT |
0.5 |
VCC+0.5 |
V |
| Power Supply Voltage *1 |
VCC |
0.5 |
+4.0 |
V |
| A9, OE, and RESET *1, *3 |
VIN |
0.5 |
+12.5 |
V |
MBM29LV160TM/BM 90 Features
• 0.23 mm Process Technology
• Single 3.0 V read, program and erase Minimizes system level power requirements
• Industry-standard pinouts
-48-pin TSOP (1) (Package suffix: TN - Normal Bend Type)
-48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance 90 ns maximum access time
• Sector erase architecture
-One 16K bytes, two 8K bytes, one 32K bytes, and thirty-one 64K bytes sectors in byte mode
-One 8K words, two 4K words, one 16K words, and thirty-one 32K words sectors in word mode
-Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
-T = Top sector
-B = Bottom sector
• Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms Automatically program and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion
• Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode
• Program Suspend/Resume Suspends the program operation to allow a read in another address
• Low VCC write inhibit £ 2.5 V
• Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector Protection Hardware method disables any combination of sectors from program or erase operations
• Sector Protection Set function by Extended sector protect command
• Fast Programming Function by Extended Command
• Temporary sector unprotection
-Temporary sector unprotection via the RESET pin
-This feature allows code changes in previously locked sectors
• In accordance with CFI (Common Flash Memory Interface)
• Single 3.0 V read, program and erase Minimizes system level power requirements
• Industry-standard pinouts
-48-pin TSOP (1) (Package suffix: TN - Normal Bend Type)
-48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance 90 ns maximum access time
• Sector erase architecture
-One 16K bytes, two 8K bytes, one 32K bytes, and thirty-one 64K bytes sectors in byte mode
-One 8K words, two 4K words, one 16K words, and thirty-one 32K words sectors in word mode
-Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
-T = Top sector
-B = Bottom sector
• Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms Automatically program and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion
• Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode
• Program Suspend/Resume Suspends the program operation to allow a read in another address
• Low VCC write inhibit £ 2.5 V
• Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector Protection Hardware method disables any combination of sectors from program or erase operations
• Sector Protection Set function by Extended sector protect command
• Fast Programming Function by Extended Command
• Temporary sector unprotection
-Temporary sector unprotection via the RESET pin
-This feature allows code changes in previously locked sectors
• In accordance with CFI (Common Flash Memory Interface)
MBM29LV160TM/BM 90 Connection Diagram
MBM100A6
PDF/DataSheet Download
- Datasheet: MBM100A6
- File Size: 79491 KB
- Manufacturer: HITACHI [Hitachi Semiconductor]
- Click here to Download
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