Purchase MBM29XL12DF-70/80, In-stock MBM29XL12DF-70/80 From SeekIC.
Part Number: MBM29XL12DF-70/80
Description: The MBM29XL12DF is 128M-bit, 3.0 V-only Page mode and dual operation Flash memory organized as 8M word...
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MBM29XL12DF-70/80
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DataSheet
General Description
MBM29XL12DF-70/80 General Description
The MBM29XL12DF is 128M-bit, 3.0 V-only Page mode and dual operation Flash memory organized as 8M words by 16 bits or 4M words by 32 bits. The device is offered in 90-pin SSOP and 96-ball FBGA packages. This device is designed to be programmed in-system with the standard system 3.0 V Vcc supply. 12.0 V Vpp and 5.0 V Vcc are not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers.
MBM29XL12DF-70/80 Maximum Ratings
| Parameter |
Conditions |
Rating |
Units | |
|
Min |
Max | |||
| Storage Temperature |
Tstg |
55 |
+125 |
°C |
| Ambient Temperature with Power Applied |
TA |
40 |
+85 |
°C |
| Voltage with Respect to Ground All Pins except A9, OE, RESET *1, *2 |
VIN, VOUT |
0.5 |
VCC+0.5 |
V |
| Power Supply Voltage *1 |
VCC |
0.5 |
+4.0 |
V |
| A9, OE, and RESET *1, *3 |
VIN |
0.5 |
+13.0 |
V |
MBM29XL12DF-70/80 Features
• 0.17 mm Process Technology
• Single 3.0 V Read, Program and Erase Minimized system level power requirements
• Simultaneous Read/Write (Program and Erase) Operations (Dual Bank)
• FlexBankTM *1
-Bank A: 16 Mbit (4K words ´8 and 32K words ´31)
-Bank B: 48 Mbit (32K words ´96)
-Bank C: 48 Mbit (32K words ´96)
-Bank D: 16 Mbit (4K words ´8 and 32K words ´31)
• High Performance Page Mode
-25 ns maximum page access time at VCC = 3.0 V to 3.6 V(70 ns random access time)
-30 ns maximum page access time at VCC = 2.7 V to 3.1 V(80 ns random access time)
• 8 Words Page (´16) / 4 Double Words Page (´32) Size
• Compatible with JEDEC-Standard Commands Uses same software commands as E2PROMs
• Compatible with JEDEC-standard World-wide Pinouts
-90-pin SSOP (Package Suffix : PFV)
-96-ball FBGA (Package Suffix : PBT)
• Minimum 100,000 Program/Erase Cycles
• Sector Erase Architecture
-Eight 4K words, two hundred fifty -four 32K words, and eight 4K words sectors
-Any combination of sectors can be concurrently erased. Also supports full chip erase
• Dual Boot Block 16 by 4K words bootblock sectors, 8 at the top of the address range and 8 at the bottom of the address range
• HiddenROM Region
-128 words of HiddenROM region by using device address of word mode 000000h to 00007Fh (double word
-mode: 000000h to 00003Fh) accessible through a "HiddenROM Enable" command sequence
-Factory serialized and protected to provide a secure electronic serial number (ESN)
• Write Protect Pin (WP)
-Write Protect (WP) function allows protection of "outermost" 2´ 4K words on both ends of boot sectors,
-regardless of sector protection/unprotection status
• Accelerate Pin (ACC) At VACC, increases program performance
• Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector
• Embedded ProgramTM *2 Algorithms Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit Feature for detection of program or erase cycle completion
• Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode When addresses remain stable, the device automatically switches itself to low power mode.
• Low VCC Write Inhibit £ VLKO
• Program Suspend/Resume Suspends the program operation to allow a read in another word
• Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device
• In accordance with CFI (Common Flash Memory Interface)
• Hardware Reset Pin (RESET) Hardware method to reset the device for reading array data
• New Sector Protection Persistent Sector Protection Password Sector Protection
• Hardware Sector Group Protection Hardware method disables any combination of sectors from program or erase operation
• Single 3.0 V Read, Program and Erase Minimized system level power requirements
• Simultaneous Read/Write (Program and Erase) Operations (Dual Bank)
• FlexBankTM *1
-Bank A: 16 Mbit (4K words ´8 and 32K words ´31)
-Bank B: 48 Mbit (32K words ´96)
-Bank C: 48 Mbit (32K words ´96)
-Bank D: 16 Mbit (4K words ´8 and 32K words ´31)
• High Performance Page Mode
-25 ns maximum page access time at VCC = 3.0 V to 3.6 V(70 ns random access time)
-30 ns maximum page access time at VCC = 2.7 V to 3.1 V(80 ns random access time)
• 8 Words Page (´16) / 4 Double Words Page (´32) Size
• Compatible with JEDEC-Standard Commands Uses same software commands as E2PROMs
• Compatible with JEDEC-standard World-wide Pinouts
-90-pin SSOP (Package Suffix : PFV)
-96-ball FBGA (Package Suffix : PBT)
• Minimum 100,000 Program/Erase Cycles
• Sector Erase Architecture
-Eight 4K words, two hundred fifty -four 32K words, and eight 4K words sectors
-Any combination of sectors can be concurrently erased. Also supports full chip erase
• Dual Boot Block 16 by 4K words bootblock sectors, 8 at the top of the address range and 8 at the bottom of the address range
• HiddenROM Region
-128 words of HiddenROM region by using device address of word mode 000000h to 00007Fh (double word
-mode: 000000h to 00003Fh) accessible through a "HiddenROM Enable" command sequence
-Factory serialized and protected to provide a secure electronic serial number (ESN)
• Write Protect Pin (WP)
-Write Protect (WP) function allows protection of "outermost" 2´ 4K words on both ends of boot sectors,
-regardless of sector protection/unprotection status
• Accelerate Pin (ACC) At VACC, increases program performance
• Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector
• Embedded ProgramTM *2 Algorithms Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit Feature for detection of program or erase cycle completion
• Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode When addresses remain stable, the device automatically switches itself to low power mode.
• Low VCC Write Inhibit £ VLKO
• Program Suspend/Resume Suspends the program operation to allow a read in another word
• Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device
• In accordance with CFI (Common Flash Memory Interface)
• Hardware Reset Pin (RESET) Hardware method to reset the device for reading array data
• New Sector Protection Persistent Sector Protection Password Sector Protection
• Hardware Sector Group Protection Hardware method disables any combination of sectors from program or erase operation
MBM29XL12DF-70/80 Connection Diagram
MBM100A6
PDF/DataSheet Download
- Datasheet: MBM100A6
- File Size: 79491 KB
- Manufacturer: HITACHI [Hitachi Semiconductor]
- Click here to Download
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