MFG:MOT Package Cooled:PLCC28 D/C:07/08+
MFG: MOT
Package Cooled: PLCC28
D/C: 07/08+
Description: The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential ou...
The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.
` 950ps Max. D to Output
`850ps Max. LEN to Output
` Differential Outputs
` Asynchronous Master Reset
` Dual Latch-Enables
` Extended 100E VEERange of -4.2V to -5.4
` 75k Input Pulldown Resistors
MC100E156
PDF/DataSheet Download
The MC100E155 contains six 2:1 multiplexers followed by transparent latches with single-ended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data iscontrolled by the multiplexer select control, SEL. A logic HIGH o...
IC REGISTER 6BIT D ECL 28-PLCC
IC REGISTER 6BIT D ECL 28-PLCC
The MC100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset (MR...
IC LATCH 6BIT D 5V ECL 28-PLCC
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