MFG:ON Package Cooled:00+ D/C:SOP
MFG: ON
Package Cooled: 00+
D/C: SOP
Description: The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are contro...
The MC10E/100E157 contains four 2:1 multiplexers with differential outputs. The output data are controlled by the individual Select (SEL) inputs. The individual select control makes the devices well suited for random logic designs.
MC100E157
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The MC100E156FN contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). ...
The MC100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A ...
The MC100E155 contains six 2:1 multiplexers followed by transparent latches with single-ended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data iscontrolled by the multiplexer select control, SEL. A logic HIGH o...
IC REGISTER 6BIT D ECL 28-PLCC
IC REGISTER 6BIT D ECL 28-PLCC
The MC100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset (MR...
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