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Part Number: MC100EP31
Description: The MC10/100EP31 is a D flipflop with set and reset. The device is pin and functionally equivalent to the EL31 and L...
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MC100EP31
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DataSheet
General Description
MC100EP31 General Description
The MC10/100EP31 is a D flipflop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices.With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous,level triggered signals. Data enters the master portion of the flipflop when CLK is low and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK.
The 100 Series contains temperature compensation.
MC100EP31 Maximum Ratings
| Symbol |
Parameter |
Condition 1 |
Condition 2 |
Rating |
Units |
| VCC |
PECL Mode Power Supply |
VEE= OV |
6 |
V | |
| VEE | NECL Mode Power Supply |
VCC= OV |
-6 | V | |
| VI |
|
VEE=OV VCC=OV |
VIVCC
|
6 -6 |
V V |
| Iout | Output Current | Continuous Surge |
50 100 |
mA mA | |
| TA | Operating Temperature Range | 40 to +85 | °C | ||
| TSTY | Storage Temperature Range | 65 to +150 | °C | ||
| JA |
Thermal Resistance (JunctiontoAmbient) |
0 LFPM 500 LFPM |
8 TSSOP 8 TSSOP |
190 130 |
°C/W °C/W |
| JC | Thermal Resistance (JunctiontoCase) | std bd | 8 TSSOP | 40 to 41 | °C/W |
| JA |
Thermal Resistance (JunctiontoAmbient) |
0 LFPM 500 LFPM |
8 SOIC 8 SOIC |
185 140 |
°C/W °C/W |
| JC | Thermal Resistance (JunctiontoCase) | std bd | 8 SOIC | 41 to44 | °C/W |
| Tsol |
Wave Solder |
<2 to 3 sec @ 248°C |
265 |
°C |
MC100EP31 Features
•340 ps Typical Propagation Delay
•Maximum Frequency > 3 GHz Typical
•PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE= 0 V
•NECL Mode Operating Range: VCC = 0 V with VEE= 3.0 V to 5.5 V
•Open Input Default State
•Q Output Will Default LOW with Inputs Open or at VEE
•Maximum Frequency > 3 GHz Typical
•PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE= 0 V
•NECL Mode Operating Range: VCC = 0 V with VEE= 3.0 V to 5.5 V
•Open Input Default State
•Q Output Will Default LOW with Inputs Open or at VEE
MC100EP31 Typical Application
AN1404ECLinPS Circuit Performance at NonStandard VIH Levels
AN1405ECL Clock Distribution Techniques
AN1406Designing with PECL (ECL at +5.0 V)
AN1504Metastability and the ECLinPS Family
AN1568Interfacing Between LVDS and ECL
AN1650Using WireOR Ties in ECLinPS Designs
AN1672The ECL Translator Guide
AND8001Odd Number Counters Design
AND8002Marking and Date Codes
AND8009ECLinPS Plus Spice I/O Model Kit
AND8020Termination of ECL Logic Devices
AN1405ECL Clock Distribution Techniques
AN1406Designing with PECL (ECL at +5.0 V)
AN1504Metastability and the ECLinPS Family
AN1568Interfacing Between LVDS and ECL
AN1650Using WireOR Ties in ECLinPS Designs
AN1672The ECL Translator Guide
AND8001Odd Number Counters Design
AND8002Marking and Date Codes
AND8009ECLinPS Plus Spice I/O Model Kit
AND8020Termination of ECL Logic Devices
MC100EP31 Connection Diagram
MC100EP31
PDF/DataSheet Download
- Datasheet: MC100EP31
- File Size: 73728 KB
- Manufacturer: ON SEMICONDUCTOR
- Click here to Download
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