MC100EP40

The MC100EP40 is a three-state phase-frequency detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate of the R and V inputs should be less than 5 ns. The device is designed to work with a 3.3 V / 5 V power supply.

When Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and
integrated provide an error voltage for control of a VCO.

When Reference (R) and Feedback (FB) inputs are 80 ps or less in phase difference, the Phase Lock Detect pin will indicate lock by a high state (V_OH). The V_TX (V_TR, VTR, V_TFB, VTFB, ) pins offer an internal termination network for 50 line impedance environment shown in Figure 2. An external sinking supply of V_CC-2 V is required on V_TX pin(s). If you short the two differential V_TR and VTR, (or V_TFB and VTFB, ) together, you provide a 100   termination resistance that is compatible with LVDS signal receiver termination. For more information on termination of logic devices, see AND8020.

The V_BB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V_BB as a switching reference voltage. V_BB may also rebias AC coupled inputs. When used, decouple VBB and V_CC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V_BB should be left open.

For more information on Phase Lock Loop operation, refer to AND8040.

Special considerations are required for differential inputs under No Signal conditions to prevent instability.