MC100EP445 General Description
MC100EP445 Maximum Ratings
MC100EP445 Features
•300 ps Propagation Delay
•5.0 Gb/s Typical Data Rate for CLKSEL LOW Mode
•Differential Clock and Serial Inputs
•VBBOutput for Single-Ended Input Applications
•Asynchronous Data Synchronization (SYNC)
•Asynchronous Master Reset (RESET)
•PECL Mode Operating Range: VCC= 3.0 V to 5.5 Vwith VEE= 0 V
•NECL Mode Operating Range: VCC= 0 Vwith VEE= -3.0 V to -5.5 V
•Open Input Default State
•CLK ENABLE Immune to Runt Pulse Generation
MC100EP445 Typical Application
The MC10/100EP445 is an integrated 1:8 serial to parallel converter with two modes of operation selected by CKSEL (Pin 7). CKSEL HIGH mode only latches data on the rising edge of the input CLK and CKSEL LOW mode latches data on both the rising and falling edge of the input CLK. CKSEL LOW is the open default state. Either of the two differential input serial data path provided for this device, SINA and SINB, can be chosen with the SINSEL pin (pin 25). SINA is the default input path when SINSEL pin is left floating. Because of internal pull-downs on the input pins, all input pins will default to logic low when left open.The two selectable serial data paths can be used for loop-back testing as well as the bit error testing. Upon power-up, the internal flip-flops will attain a random state. To synchronize multiple flipflops in the device, the Reset (pin 1) must be asserted. The reset pin will disable the internal clocksignalirrespective of the CKEN state (CKEN disables the internal clock circuitry). The device will grab the first stream of data after the falling edgeof RESET
MC100EP445 Connection Diagram
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