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Part Number: MC100EP51

 

 

 

 

Description: The MC10/100EP51 is a differential clock D flipflop with reset. The device is functionally equivalent to the EL51 and L...


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MC100EP51 General Description


The MC10/100EP51 is a differential clock D flipflop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.

The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flipflop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop.

The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLK input will be biased at VCC/2.

The 100 Series contains temperature compensation.

MC100EP51 Maximum Ratings

Symbol
Parameter
Condition1 Condition2
Rating
Unit
VCC
PECL Mode Power Supply VEE = 0 V  
6
V
VEE
NECL Mode Power Supply VCC=0 V  
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC=0 V
VI VCC
VI VEE
-6
6
V
V
Iout
Output Current  Continuous
Surge
 
50
100
mA
mA
TA
Operating Temperature Range    
40 to +85
Tstg
Storage Temperature Range    
65 to +150
JA
Thermal Resistance (Junction to Ambient) 0 LFPM
500 LFPM
8 SOIC
8 SOIC
190
130
/W
/W
JC
Thermal Resistance (Junction to Case) std bd 8 SOIC
41 to 44
/W
JA Thermal Resistance (Junction to Ambient) 0 LFPM
500 LFPM
8 TSSOP
8 TSSOP
185
140
/W

/W
JC Thermal Resistance (Junction to Case) std bd 8 TSSOP
41 to 44
/W
Tsol
Wave Solder <2 to 3 sec @ 248°C  
265

MC100EP51 Features

• 350 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = 3.0 V to 5.5 V
• Open Input Default State
• Safety Clamp on Inputs

MC100EP51 datasheet

MC100EP51
PDF/DataSheet Download

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