MC100EPT21

The MC100EPT21 is a Differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The small outline 8−lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal.

The V_BB output allows this EPT21 to be cap coupled in either single−ended or differential input mode. When single−ended cap coupled, VBB output is tied to the D input and D is driven for a non−inverting buffer, or V_BB output is tied to the D input and D is driven for an inverting buffer. When cap coupled differentially, V_BB output is connected through a resistor to each input pin. If used, the V_BB pin should be bypassed to V_CC via a 0.01 F capacitor. For additional information see AND8020/D. For a single−ended direct connection use an external voltage reference source such as a resistor divider. Do not use V_BB for a single−ended direct connection or port to another device.