MC100LVEL39DW

The MC100LVEL39DW is one member of the MC100LVEL39 family which is designed as the low skew ÷2, ÷4/6 clock generation chip that designed explicitly for low skew clock generation applications. MC100LVEL39DW can be driven by either a differential or single-ended LVECL or, if positive power supplies are used, LVPECL input signal. And an internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

Features of the MC100LVEL39DW are:(1)50ps Output-to-Output Skew; (2)Synchronous Enable/Disable; (3)Master Reset for Synchronization; (4)75kW Internal Input Pulldown Resistors; (5)>1500V ESD Protection; (6)Low Voltage VEE Range of -3.0 to -3.8V.

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