MFG:ON Package Cooled:PLCC
MFG: ON
Package Cooled: PLCC
Description: The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential ou...
The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.
MC1000
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The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date of MC10E/100E156is controlled by the multiplexer select contr...
The MC10E155FN is one member of the MC10E155 family which is designed as the 6 bit 2:1 mux-latch that contains six 2:1 multiplexers followed by transparent latches with single-ended outputs. Features of MC10E155FN are:(1)850ps max. LEN to output; (2)825ps ma...
The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single-ended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data of MC10E/100E155is controlled by the multiplexer select control...
IC REGISTER 6BIT D ECL 5V 28PLCC
The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset...
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