MC10E451

The MC10E/100E451 contains six D-type flip-flops with single-ended outputs and differential data inputs. The common clock input is alsodifferential. The registers are triggered by a positive transition of the positive clock (CLK) input.

A HIGH on the Master Reset (MR) input resets all Q outputs to LOW. The VBB output is intended for use as a reference voltage for single-ended reception of ECL signals to that device only. When using forthis purpose, it is recommended that V_BB is decoupled to V_CC via a0.0µF capacitor.
The differential input structures are clamped so that the inputs ofunused registers can be left open without upsetting the bias network of the device. The clamping action will assert the D and the CLK sides of theinputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in anoutput which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5V below V_CC.