MC14035B

The MC14035B 4bit shift register is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure.

It consists of a 4stage clocked serialshift register with synchronous parallel inputs and buffered parallel outputs. The Parallel/Serial (P/S) input allows serialright shifting of data or synchronous parallel loading via inputs DP0 thru DP3. The True/Complement (T/C) input determines whether the outputs display the Q or Q outputs of the flipflop stages. JK logic forms the serial input to the first stage. With the J and K inputs connected together they operate as a serial "D" input.

This device may be effectively used for shiftright/shiftleft registers, paralleltoserial/serialtoparallel conversion, sequence generation, up/ down Johnson or ring counters, pseudorandom code generation, frequency and phase comparators, sample and hold registers, etc . . .
• 4Stage Clocked SerialShift Operation
• Synchronous Parallel Loading of all Four Stages
• JK Serial Inputs on First Stage
• Asynchronous True/Complement Control of all Outputs
• Fully Static Operation
• Asynchronous Master Reset
• Data Transfer Occurs on the PositiveGoing Clock Transition
• No Limit on Clock Rise and Fall Times
• All Inputs are Buffered
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range