MC143416

The MC143416 dual 16-bit linear codec-filter is a single-chip implementation of the data conversion interface required to design high-speed modems meeting a wide range of standards such as ITU-T V.34 and V.90 modem. It includes two high performance analog-to-digital (A/D) and digital-to-analog (D/A) data converters.The device performs all filtering operations related to the conditioning and sample rate conversion of signals to and from the data interface.Output from both codecs (COder/DECoder) is in 16-bit 2s complement format.

Features of the MC143416 are:(1)fully-differential analog circuit design for lowest noise;(2)two high performance 16-bit sigma-delta a/d and d/a converters;(3)band-pass and low-pass filtering for both codecs is performed on-chip;(4)power monitor circuit;(5)single 5 V±5% power supply;(6)two configurable serial ports;(7)on-chip precision reference voltage;(8)bandwidth is 0.425*FS; (9)no external filtering required because of flat response over passband;(10)capable of providing the analog front end for wide range of modem standards.

The absolute maximum ratings of the MC143416 can be summarized as:(1)operating temperature range:-40 to +85°C;(2)storage temperature range: -85 to 150°C;(3)DC supply voltage:-0.5 to +6.0V;(4)voltage on any analog input or output pin:AGND-0.3 to Vdd +0.3V;(5)voltage on any digital input or output pin:DGND-0.3 to Vdd +0.3V.This device contains protection circuitry to guard against damage due to high static voltages or electric fields.However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit.This pin turns off any activity in the MC143416 except the power monitor function by stopping the oscillator. After any assertion of the PDI pin, a 10 ms period is required to resume functional operation. This time constraint is needed for the crystal oscillator to start up and stabilize to its defined operating point. It is mandatory to apply a hardware reset after this oscillator startup phase. Alternatively, a software reset can be applied after this startup phase and after making sure the serial interface framing logic has synced up to the host control/data frame.