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MFG:MOT  Package Cooled:SOP  

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Part Number: MC14557B

 

MFG: MOT

Package Cooled: SOP

 

Description: The MC14557B is a static clocked serial shift register whose length may be programmed to be any number...


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MC14557B General Description


The MC14557B is a static clocked serial shift register whose length may be programmed to be any number of bits between 1 and 64. The number of bits selected is equal to the sum of the subscripts of the enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus one. Serial data may be selected from the A or B data inputs with the A/B select input. This feature is useful for recirculation purposes. A Clock Enable (CE) input is provided to allow gating of the clock or negative edge clocking capability.

The device can be effectively used for variable digital delay lines or simply to implement odd length shift registers.
• 164 Bit Programmable Length
• Q and Q Serial Buffered Outputs
• Asynchronous Master Reset
• All Inputs Buffered
• No Limit On Clock Rise and Fall Times
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Lowpower TTL Loads or one Lowpower Schottky TTL Load Over the Rated Temperature Range

MC14557B Maximum Ratings

Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
55 to +125
°C
Tstg
Storage Temperature Range
65 to +150
°C
TL
Lead Temperature
(8Second Soldering)
260
°C

2. Maximum Ratings are those values beyond which damage to the device may occur.
3. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/°C From 65°C To 125°C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD.  Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

MC14557B Connection Diagram

MC14557B  Connection Diagram

MC14557B datasheet

MC14557B
PDF/DataSheet Download

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