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Part Number: MC54C4040A
Description: The MC54/74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatibl...
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MC54C4040A
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DataSheet
General Description
MC54C4040A General Description
The MC54/74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 12 masterslave flipflops. The output of each flipflop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negativegoing edge of the Clock input. Reset is asynchronous and activehigh.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.
MC54C4040A Maximum Ratings
| Symbol | Parameter | Value | Unit |
| vcc | DC Supply Voltage (Referenced to GND) | 0.5 to +7.0 | V |
| VIN | DC Input Voltage (Referenced to GND) | 0.5 to VCC + 0.5 | V |
| VOUT | DC Output Voltage (Referenced to GND) | 0.5 to VCC + 0.5 | V |
| LIN | DC Input Current, per Pin | ±20 | mA |
| IOUT | DC Onput Current, per Pin | ±25 | mA |
| ICC | DC Supply Current Per Supply Pin | ±50 | mA |
| PD | Power dissipation in still air piastic DIP SOIC package |
750 500 450 |
mW |
| TSTG | Storage Temperature | 65 to +150 | °C |
| TL | Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) |
260 300 |
°C |
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating - Plastic DIP: 10 mW/ from 65to 125
Ceramic DIP: 10 mW/ from 100 to 125
SOIC Package: 7 mW/ from 65 to 125
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
MC54C4040A Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gate
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gate
MC54C4040A Connection Diagram
MC500
PDF/DataSheet Download
- Datasheet: MC500
- File Size: 337495 KB
- Manufacturer: ETC [ETC]
- Click here to Download
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