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Part Number: MC68302FC20

 

MFG: MOT

Package Cooled: QFP

D/C: 08+

Description: The MC68302 integrated multiprotocol processor (IMP) is a very large-scale integration (VLSI) device i...


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MC68302FC20 General Description


The MC68302 integrated multiprotocol processor (IMP) is a very large-scale integration (VLSI) device incorporating the main building blocks needed for the design of a wide variety of controllers. The device is especially suitable to applications in the communications industry. The IMP is the first device to offer the benefits of a closely coupled, industry-standard M68000 microprocessor core and a flexible communications architecture. The IMP may be configured to support a number of popular industry interfaces, including those for the Integrated Services Digital Network (ISDN) basic rate and terminal adaptor applications. Concurrent operation of different protocols is easily achieved through a combination of architectural and programmable features. Data concentrators, line cards, modems, bridges, and gateways are examples of suitable applications for this device.

The IMP is a high-density complementary metal-oxide semiconductor (HCMOS) device consisting of an M68000 microprocessor core, a system integration block (SIB), and a communications
processor (CP).

MC68302FC20 Features

• On-Chip HCMOS MC68000/MC68008 Core Supporting a 16- or 8-Bit M68000 Family- System
• IB Including:
  -Independent Direct Memory Access (IDMA) Controller with Three Handshake Signals: DREO, DACK , and DONE .
  -Interrupt Controller with Two Modes of Operation
  -Parallel Input/Output (I/O) Ports, Some with Interrupt Capability
  -On-Chip 1152-Byte Dual-Port RAM
  -Three Timers Including a Watchdog Timer
  -Four Programmable Chip-Select Lines with Wait-State Generator Logic
  -Programmable Address Mapping of the Dual-Port RAM and IMP Registers
  -On-Chip Clock Generator with Output Signal
  -System Control:
     Bus Arbitration Logic with Low-Interrupt Latency Support
     System Status and Control Logic
     Disable CPU Logic (M68000)
     Hardware Watchdog
     Low-Power (Standby) Modes
     Freeze Control for Debugging
     DRAM Refresh Controller

• CP Including:
  -Main Controller (RISC Processor)
  -Three Independent Full-Duplex Serial Communications Controllers (SCCs)
  -Supporting Various Protocols:
     High-Level/Synchronous Data Link Control (HDLC/SDLC)
     Universal Asynchronous Receiver Transmitter (UART)
     Binary Synchronous Communication (BISYNC)
     Synchronous/Asynchronous Digital Data Communications Message
     Protocol (DDCMP)
     Transparent Modes
     V.110 Rate Adaption
  -Six Serial DMA Channels for the Three SCCs
  -Flexible Physical Interface Accessible by SCCs Including:
     Motorola Interchip Digital Link (IDL)
     General Circuit Interface (GCI, also known as IOM3 -2)
     Pulse Code Modulation (PCM) Highway Interface
     Nonmultiplexed Serial Interface (NMSI) Implementing Standard Modem Signals
  -SCP for Synchronous Communication
  -Two Serial Management Controllers (SMCs) To Support IDL and GCI AuxiliaryChannels

MC68302FC20 datasheet

MC68302FC20
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