MC6850

The MC6850 asynchronous communications interface adapter provides the data formatting and control to interface serial asynchronous data communications information to bus organized systems such as the MC6800 microprocessing unit.The bus interface of the MC6850 includes select, enable, read,write, interrupt and bus interface logic to allow data transfer over an 8-bit bidireciional data bus. The parallel data of the bus system is serially transmitted and received by the asynchronous data interface, with proper formatting and error checking. The functional of MC6850 configuration of the ACIA is programmed via the data bus during system initialization. A programmable Control Register provides variable word lengths, clock division ratios, transmit control, receive control, and interrupt control. For peripheral or modem operation, three control lines are provided. These lines of MC6850 allow the ACIA to interface directly with the MC6860L 0-600 bps digital modem.

Features of the MC6850 are:(1)8- and 9-bit transmission;(2)optional even and odd parity;(3)parity, overrun and framing error checking;(4)programmable control register;(5)optional÷1,÷16, and÷64 clock modes;(6)up to 1.0 mbps transmission;(7)false start bit deletion;(8)peripheral modem control functions;(9)double buffered;(10)one- or two-stop bit operation.

The absolute maximum ratings of the MC6850 can be summarized as:(1)supply voltage:-0.3 to +7.0V;(2)operating temperature:-40 to +85°C;(3)storage temperature:-55 to +150°C;(4)input voltage:-0.3 to +7.0.This device contains circuitry to protect the inputs  against  damage  due  to  high  static voltages or electric fields; however, it is advised that normal precautions be taken  to avoid application of any voltage higher than maximum  rated  voltages to  this  high impedance circuit. Reliability of operation is enhanced if unused inputs are Med to an appropriate logic voltage level le.g., either VSS or Vcc.A typical transmitting sequence consists of reading the ACIA Status Register either as a result of an interrupt or in the ACIA's turn in a polling sequence. A character may be written into the Transmit Data Register if the status read operation has indicated that the Transmit Data Register is empty.This character is transferred to a Shift Register where it is serialized and transmitted from the Transmit Data output preceded by a start bit and followed by one or two stop bits Internal parity lodd or even) can be optionally added to the character and will occur between the last data bit and the first stop bit.