MC68EN302 Features
• Full Complement of Existing Three SCC's Plus Ethernet Channel
• Ethernet Channel Fully Compliant with IEEE 802.3 Specification.
• Supports Data Rates up to 10 Mbps.
• Supports the "68302" Style Programming Model.
• On-Chip Descriptors Lower Processor Bus Bandwidth Requirements.
• Separate 128 Byte FIFOs for Transmit and Receive.
• Automatic Internal Retransmission (which Frees the Processor Bus).
• Automatic Internal Flushing of Receive FIFO During Collisions (which Frees the Processor Bus).
• Dynamic Bus Sizing Support for 8-Bit Devices
• Glueless Dynamic RAM Controller without External Bus Master
• Address Muxing Support for External Bus Masters Using DRAM Controller
• Fully IEEE 1149.1 JTAG Compliant
• 144 TQFP Package for Up to 25 MHz
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