Purchase MC68HC705JJ7, In-stock MC68HC705JJ7 From SeekIC.
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MC68HC705JJ7
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Suppliers
DataSheet
General Description
MC68HC705JJ7 Maximum Ratings
| Rating | Symbol | Value | Unit |
| Supply voltage | VDD | 0.3 to +7.0 | V |
| Bootloader/self-check mode (IRQ/VPP pin only) |
VIn | VSS 0.3 to 1 | V |
| Current drain per pin excluding VDD and VSS | I | 25 | mA |
| Operating junction temperature | TJ | +150 | °C |
| Storage temperature range | Tstg | 65 to +150 | °C |
MC68HC705JJ7 Features
• Low-cost, M68HC05 core MCU in 20-pin package
(MC68HC705JJ7) or 28-pin package (MC68HC705JP7)
• 6160 bytes of user EPROM, including 16 bytes of user vectors
• 224 bytes of low-power user random-access memory (RAM)
• 64 bits of personality EPROM (serial access)
• 16-bit programmable timer with input capture and output compare
• 15-stage core timer, including 8-bit free-running counter
and 4-stage selectable real-time interrupt generator
• Simple serial input/output port (SIOP) with interrupt capability
• Two voltage comparators, one of which can be combined with the
16-bit programmable timer to create a 4-channel, single-slope
analog-to-digital (A/D) converter
• Output of voltage comparator can drive port pin PB4 directly under
software control
• 14 input/output (I/O) lines (MC68HC705JJ7) or 22 I/O lines
(MC68HC705JP7), including high-source/sink current capability
on 6 I/O pins (MC68HC705JJ7) or 14 I/O pins (MC68HC705JP7)
• Programmable 8-bit mask option register (MOR) to select mask
options found in read-only memory (ROM) based versions
• MOR selectable software programmable pulldowns on all I/O pins
and keyboard scan interrupt on four I/O pins
• Software mask and request bit for IRQ interrupt with MOR
selectable sensitivity on IRQ interrupt (edge- and level-sensitive or edge-only)
• On-chip oscillator with device option of crystal/ceramic resonator
or resistor-capacitor (RC) operation and MOR selectable shunt
resistor, 2 M by design
• Internal oscillator for lower-power operation, approximately
100 kHz (500 kHz selected as device option)
• EPROM security bit(1) to aid in locking out access to
programmable EPROM array
• MOR selectable computer operating properly (COP) watchdog system
• Power-saving stop and wait mode instructions (MOR selectable
STOP conversion to halt and option for fast 16-cycle restart
and power-on reset)
• On-chip temperature measurement diode
• MOR selectable reset module to reset central processor unit
(CPU) in low-voltage conditions
• Illegal address reset
• Internal steering diode and pullup device on RESET pin to VDD
(MC68HC705JJ7) or 28-pin package (MC68HC705JP7)
• 6160 bytes of user EPROM, including 16 bytes of user vectors
• 224 bytes of low-power user random-access memory (RAM)
• 64 bits of personality EPROM (serial access)
• 16-bit programmable timer with input capture and output compare
• 15-stage core timer, including 8-bit free-running counter
and 4-stage selectable real-time interrupt generator
• Simple serial input/output port (SIOP) with interrupt capability
• Two voltage comparators, one of which can be combined with the
16-bit programmable timer to create a 4-channel, single-slope
analog-to-digital (A/D) converter
• Output of voltage comparator can drive port pin PB4 directly under
software control
• 14 input/output (I/O) lines (MC68HC705JJ7) or 22 I/O lines
(MC68HC705JP7), including high-source/sink current capability
on 6 I/O pins (MC68HC705JJ7) or 14 I/O pins (MC68HC705JP7)
• Programmable 8-bit mask option register (MOR) to select mask
options found in read-only memory (ROM) based versions
• MOR selectable software programmable pulldowns on all I/O pins
and keyboard scan interrupt on four I/O pins
• Software mask and request bit for IRQ interrupt with MOR
selectable sensitivity on IRQ interrupt (edge- and level-sensitive or edge-only)
• On-chip oscillator with device option of crystal/ceramic resonator
or resistor-capacitor (RC) operation and MOR selectable shunt
resistor, 2 M by design
• Internal oscillator for lower-power operation, approximately
100 kHz (500 kHz selected as device option)
• EPROM security bit(1) to aid in locking out access to
programmable EPROM array
• MOR selectable computer operating properly (COP) watchdog system
• Power-saving stop and wait mode instructions (MOR selectable
STOP conversion to halt and option for fast 16-cycle restart
and power-on reset)
• On-chip temperature measurement diode
• MOR selectable reset module to reset central processor unit
(CPU) in low-voltage conditions
• Illegal address reset
• Internal steering diode and pullup device on RESET pin to VDD
MC68HC705JJ7 Connection Diagram
MC68HC705JJ7
PDF/DataSheet Download
- Datasheet: MC68HC705JJ7
- File Size: 3172320 KB
- Manufacturer: MOTOROLA [Motorola, Inc]
- Click here to Download
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