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MC68HC812A4

Features: • Low-power, high-speed M68HC12 CPU• Power-saving stop and wait modes• Memory: 1024-byte RAM 4096-byte EEPROM On-chip memory mapping allows expansion to more than 5-Mbyte address space• Single-wire Background Debug® mode• Non-multiplexed address and data...

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SeekIC No. : 004416478 Detail

MC68HC812A4: Features: • Low-power, high-speed M68HC12 CPU• Power-saving stop and wait modes• Memory: 1024-byte RAM 4096-byte EEPROM On-chip memory mapping allows expansion to more than 5-Mbyte...

MC68HC812A4 Data Sheet

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Part Number:
MC68HC812A4
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2026/4/16

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Product Details

Description



Features:

• Low-power, high-speed M68HC12 CPU
• Power-saving stop and wait modes
• Memory:
1024-byte RAM
4096-byte EEPROM
On-chip memory mapping allows expansion to more than 5-Mbyte address space
• Single-wire Background Debug® mode
• Non-multiplexed address and data buses
• Seven programmable chip-selects with clock stretching (expanded modes)
• 8-channel, enhanced 16-bit timer with programmable prescaler:
All channels configurable as input capture or output compare
Flexible choice of clock source
• 16-bit pulse accumulator
• Real-time interrupt circuit
• Computer operating properly (COP) watchdog
• Clock monitor
• Phase-locked loop (PLL)
• Two enhanced asynchronous non-return-to-zero (NRZ) serial communication interfaces (SCI)
• Enhanced synchronous serial peripheral interface (SPI)
• 8-channel, 8-bit analog-to-digital converter (ATD)
• Up to 24 key wakeup lines with interrupt capability
• Available in 112-lead low-profile quad flat pack (LQFP) packagin


Pinout

Connection Diagram


Specifications

Rating
Symbol
Value
Unit
Supply voltage
VDD
VDDA
VDDX
0.3 to +6.5
V
Input voltage
VIn
0.3 to +6.5
V
Maximum current per pin
excluding VDD and VSS
IIn
± 25
mA
Storage temperature
TSTG
55 to +150
°C
VDD differential voltage
VDDVDDX
6.5
V
NOTE: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIn and VOut be constrained to the range VSS (VIn or VOut) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD).


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