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- Table of contents:
MC68QH302
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Suppliers
DataSheet
General Description
MC68QH302 Features
The main features of the MC68QH302 are as follows (new features indicated in bold):
• MC68000/MC68008 microprocessor core (may be disabled to use the IMP as a peripheral)
• Serial interface block including:
- Independent direct memory access (IDMA) controller
- Interrupt controller with two modes of operation
- Parallel I/O ports, some with interrupt capability
- On-chip 1152 bytes of dual-ported RAM
- Three timers, including a software watchdog timer
- Four programmable chip-select lines with wait-state logic
- Programmable address mapping of dual-ported RAM and IMP registers
- On-chip clock generator with an output clock signal
- System control
System control register
Bus arbitration logic with low-interrupt latency support
Hardware watchdog for monitoring bus activity
Low power (standby) modes
Disable CPU logic (M68000)
Freeze control for debugging selected on-chip peripherals
DRAM refresh controller
• CP including:
- Main controller (RISC processor)
- Three physical full-duplex serial communication controllers (SCCs) with the following protocols:
HDLC/SDLC
UART
Totally transparent
V.110
- SCC1 can support two logical HDLC or transparent channels running QH protocol
- Eight serial DMA channels dedicated to the four serial channels
- Capability to send /receive up to eight buffers/frames without M68000 core intervention
- Flexible physical interface accessible by SCCs for interchip digital link (IDL), general circuit interface (GCI, also called IOM2), pulse code modulation (PCM), and nonmultiplexed serial interface (NMSI) operation
- Serial communication port (SCP) for synchronous communication
- Serial management controllers (SMCs) for IDL and GCI channels
• Application development system available with M68302FADS.
• MC68000/MC68008 microprocessor core (may be disabled to use the IMP as a peripheral)
• Serial interface block including:
- Independent direct memory access (IDMA) controller
- Interrupt controller with two modes of operation
- Parallel I/O ports, some with interrupt capability
- On-chip 1152 bytes of dual-ported RAM
- Three timers, including a software watchdog timer
- Four programmable chip-select lines with wait-state logic
- Programmable address mapping of dual-ported RAM and IMP registers
- On-chip clock generator with an output clock signal
- System control
System control register
Bus arbitration logic with low-interrupt latency support
Hardware watchdog for monitoring bus activity
Low power (standby) modes
Disable CPU logic (M68000)
Freeze control for debugging selected on-chip peripherals
DRAM refresh controller
• CP including:
- Main controller (RISC processor)
- Three physical full-duplex serial communication controllers (SCCs) with the following protocols:
HDLC/SDLC
UART
Totally transparent
V.110
- SCC1 can support two logical HDLC or transparent channels running QH protocol
- Eight serial DMA channels dedicated to the four serial channels
- Capability to send /receive up to eight buffers/frames without M68000 core intervention
- Flexible physical interface accessible by SCCs for interchip digital link (IDL), general circuit interface (GCI, also called IOM2), pulse code modulation (PCM), and nonmultiplexed serial interface (NMSI) operation
- Serial communication port (SCP) for synchronous communication
- Serial management controllers (SMCs) for IDL and GCI channels
• Application development system available with M68302FADS.
MC68QH302
PDF/DataSheet Download
- Datasheet: MC68QH302
- File Size: 21639 KB
- Manufacturer: Motorola
- Click here to Download
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