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Part Number: MC74HC366
Description: The MC54/74HC366 is identical in pinout to the LS366. The device inputs are compatible with standard C...
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MC74HC366
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General Description
MC74HC366 General Description
The MC54/74HC366 is identical in pinout to the LS366. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device is a highspeed hex buffer with 3state outputs and two common activelow Output Enables. When either of the enables is high, the buffer outputs are placed into highimpedance states. The HC366 has inverting outputs
MC74HC366 Maximum Ratings
|
Symbol |
Parameter |
Value |
Unit |
|
VCC |
DC Supply Voltage (Referenced to GND) |
0.5 to +7.0 |
V |
|
Vin |
DC Input Voltage (Referenced to GND) |
1.5 to VCC +1.5 |
V |
|
Vout |
DC Output Voltage (Referenced to GND) |
0.5 to VCC + 0.5 |
V |
|
Iin |
DC Input Current, per Pin |
± 20 |
mA |
|
Iout |
DC Output Current, per Pin |
± 35 |
mA |
|
ICC |
DC Supply Current, VCC and GND Pins |
± 75 |
mA |
|
PD |
Power Dissipation in Still Air, Plastic or Ceramic DIP† |
750 |
mW |
|
Tstg |
Storage Temperature |
65 to + 150 |
|
|
TL |
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) (Ceramic DIP) |
260 300 |
should be restricted to the Recommended Operating Conditions.
†Derating - Plastic DIP: 10 mW/ from 65 ° to 125
Ceramic DIP: 10 mW/ from 100 ° to 125
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
MC74HC366 Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 78 FETs or 19.5 Equivalent Gates
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 78 FETs or 19.5 Equivalent Gates
MC74HC366 Connection Diagram
MC74HC366A
PDF/DataSheet Download
- Datasheet: MC74HC366A
- File Size: 154995 KB
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