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Part Number: MC74HC42

 

MFG: DIP

 

D/C: 88+

Description: The MC74HC42 is identical in pinout to the LS42. The device inputs are compatible with standard CMOS outputs; with pull...


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MC74HC42 General Description


The MC74HC42 is identical in pinout to the LS42. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The HC42 decodes a BCD Address to oneoften active low outputs. For Address inputs with a hexadecimal equivalent greater than 9, all outputs, Y0Y9, remain high (inactive).

MC74HC42 Maximum Ratings

 

Symbol Parameter Value Unit
vcc DC Supply Voltage (Referenced to GND) 0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) 0.5 to VCC + 0.5 V
VOUT DC Output Voltage (Referenced to GND) 0.5 to VCC + 0.5 V
LIN DC Input Current, per Pin ±20 mA
IOUT DC Onput Current, per Pin ±35 mA
ICC DC Supply Current Per Supply Pin ±75 mA
PD Power dissipation in still air piastic DIP
SOIC package
750
500

mW
TSTG Storage Temperature 65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
°C

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating - Plastic DIP: 10 mW/C from 65 to 125C
Ceramic DIP: 10 mW/C from 100 to 125C
SOIC Package: 7 mW/C from 65 to 125C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

MC74HC42 Features

• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 104 FETs or 26 Equivalent Gates

MC74HC42 Connection Diagram

MC74HC42  Connection Diagram

MC74HC42 datasheet

MC74HC42
PDF/DataSheet Download

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