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MFG:MOTO D/C:DIP
Part Number: MC74HC595AN
MFG: MOTO
D/C: DIP
Description: The MC74HC595A consists of an 8bit shift register and an 8bit Dtype latch with threestate parallel out...
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MC74HC595AN
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General Description
MC74HC595AN General Description
The MC74HC595A consists of an 8bit shift register and an 8bit Dtype latch with threestate parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs.
MC74HC595AN Maximum Ratings
| Symbol | Parameter | Value | Unit |
| vcc | DC Supply Voltage (Referenced to GND) | 0.5 to +7.0 | V |
| VIN | DC Input Voltage (Referenced to GND) | 0.5 to VCC + 0.5 | V |
| VOUT | DC Output Voltage (Referenced to GND) | 0.5 to VCC + 0.5 | V |
| LIN | DC Input Current, per Pin | ±20 | mA |
| IOUT | DC Onput Current, per Pin | ±35 | mA |
| ICC | DC Supply Current Per Supply Pin | ±75 | mA |
| PD | Power dissipation in still air piastic DIP SOIC package |
750 500 |
mW |
| TSTG | Storage Temperature | 65 to +150 | °C |
| TL | Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) |
260 | °C |
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating - Plastic DIP: 10 mW/C from 65 to 125C
Ceramic DIP: 10 mW/C from 100 to 125C
SOIC Package: 7 mW/C from 65 to 125C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
MC74HC595AN Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
- Improved Propagation Delays
- 50% Lower Quiescent Power
- Improved Input Noise and Latchup Immun
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
- Improved Propagation Delays
- 50% Lower Quiescent Power
- Improved Input Noise and Latchup Immun
MC74HC595AN Connection Diagram
MC74HC595AN
PDF/DataSheet Download
- Datasheet: MC74HC595AN
- File Size: 229396 KB
- Manufacturer: MOTOROLA [Motorola, Inc]
- Click here to Download
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MC74HC595A
The MC74HC595A consists of an 8bit shift register and an 8bit Dtype latch with threestate parallel outputs. The shift register of MC74HC595A accepts serial data and provides a serial output. The shift register also provides parallel data to the 8bit latch. T...
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