MC88LV926

1. Several specifications can only be measured when the MC88LV926 is in phaselocked operation. It is not
possible to have the part in phaselock on ATE (automated test equipment). Statistical characterization
techniques were used to guarantee those specifications which cannot be measured on the ATE. MC88LV926 units
were fabricated with key transistor properties intentionally varied to create a 14 cell designed experimental matrix. IC
performance was characterized over a range of transistor properties (represented by the 14 cells) in excess of the
expected process variation of the wafer fabrication area. Response Surface Modeling (RSM) techniques were
used to relate IC performance to the CMOS transistor properties over operation voltage and temperature. IC performance to each specification and fab variation were used in conjunction with Yield Surface ModelingE (YSME) methodology to set performance limits of ATE testable specifications within those which are to be guaranteed by statistical characterization. In this way, all units passing the ATE test will meet or exceed the nontested specifications limits.

2. A 470K  resistor tied to either Analog V_CC or Analog GND, as shown in Figure 2., is required to ensure no jitter
is present on the MC88LV926 outputs. This technique causes a phase offset between the SYNC input and the
Q0 output, measured at the pins. The t_PD spec describes how this offset varies with process, temperature, and
voltage. The specs were arrived at by measuring the phase relationship for the 14 lots described in note 1 while
the part was in phaselocked operation. The actual measurements were made with a 10MHz SYNC input
(1.0ns edge rate from 0.8V to 2.0V). The phase measurements were made at 1.5V. See Figure 2. for a graphical description.

3. Two specs (tRISE/FALL ^and tPULSE ^Width 2X_Q output, see AC Specifications) guarantee that the MC88LV926
meets the 33MHz and 66MHz 68060 PClock input specification.