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Part Number: MC92602
Description: The transmitter takes the data byte presented at its data input, creates a transmission character using its 8B/10B enco...
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MC92602
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DataSheet
General Description
MC92602 General Description
The transmitter takes the data byte presented at its data input, creates a transmission character using its 8B/10B encoder (if not in Ten-Bit Interface mode), and serially transmits the character out of the differential link output pads. The following sections provide a detailed description of the transmitter and its various modes of operation.
MC92602 Maximum Ratings
|
Characteristics 1 |
Symbol |
Min |
Max |
Unit |
| Core Supply Voltage |
VDD |
-0.3 |
2.2 |
V |
| PLL Supply Voltage |
AVDD |
-0.3 |
2.2 |
V |
| HSTL I/O Supply Voltage |
VDDQ |
-0.3 |
2.2 |
V |
| Link I/O Supply Voltage |
XVDD |
-0.3 |
2.2 |
V |
| HSTL Input Voltage |
Vin |
-0.3 |
VDDQ + 0.3 |
V |
| CMOS Input Voltage |
Vin |
-0.3 |
VDD + 0.3 |
V |
| Link Input Voltage |
Vin |
-0.3 |
XVDD + 0.3 |
V |
| Storage Temperature Range |
Tstg |
-55 |
150 |
|
| ESD Tolerance |
HBM |
2,000 |
- |
V |
|
MM |
200 |
- |
V |
MC92602 Features
The following are the features of the MC92602:
• General Features
- Four full-duplex differential data links.
- Selectable speed range: 1.25 Gbaud or 0.625 Gbaud.
- Rate adaption compatibility with packet data streams
- Context sensitive rate adaption during receipt of idle and data code groups
- Supports Jumbo frame lengths of up to 16K BYTES
- Supports frame bursting
- Differential reference clock input with single-ended clock input option.
- Low power, approximately 1.2W under typical conditions, while operating all transceivers at full speed.
- Unused transceiver channels may be individually disabled.
- IEEE 1149.1 JTAG support and full-speed built in self test, (BIST), functions.
- Package: 196pin MAPBGA (15x15mm body size, 1.0 mm ball pitch).
• Data Interface Features
- Internal 8B10B encoder/decoder that may be bypassed in Ten-Bit Interface mode where external coding is used.
- Double Data Rate (DDR), source synchronous, 4-bit and 5-bit HSTL Class-I parallel interfaces.
- Transmit data clock is selectable between per-channel transmit clock or channel 'A' transmit clock.
- Link-to-link synchronization supports aligned, multi-channel, word transfers. The synchronization mechanism tolerates up to 40 bit-times of link-to-link media skew.
- Selectable Idle character alignment mode enables aligned transfers with automatic realignment or unaligned data transfers (if in 10 bit mode).
- Received data may be clocked to the recovered clock or to the reference clock frequencies.
- Compatibility mode enables non-intrusive operation with packet data streams.
• Link Interface Features
- Drives 50 or 75 media (100 or 150 differential) for lengths of up to 1.5meters board/backplane, or 10 meters of coax.
- Link inputs have on-chip receiver termination and are "hot swap" compatible.
- Tolerates a frequency offset between the transmitter and receiver in excess of +250ppm.
• General Features
- Four full-duplex differential data links.
- Selectable speed range: 1.25 Gbaud or 0.625 Gbaud.
- Rate adaption compatibility with packet data streams
- Context sensitive rate adaption during receipt of idle and data code groups
- Supports Jumbo frame lengths of up to 16K BYTES
- Supports frame bursting
- Differential reference clock input with single-ended clock input option.
- Low power, approximately 1.2W under typical conditions, while operating all transceivers at full speed.
- Unused transceiver channels may be individually disabled.
- IEEE 1149.1 JTAG support and full-speed built in self test, (BIST), functions.
- Package: 196pin MAPBGA (15x15mm body size, 1.0 mm ball pitch).
• Data Interface Features
- Internal 8B10B encoder/decoder that may be bypassed in Ten-Bit Interface mode where external coding is used.
- Double Data Rate (DDR), source synchronous, 4-bit and 5-bit HSTL Class-I parallel interfaces.
- Transmit data clock is selectable between per-channel transmit clock or channel 'A' transmit clock.
- Link-to-link synchronization supports aligned, multi-channel, word transfers. The synchronization mechanism tolerates up to 40 bit-times of link-to-link media skew.
- Selectable Idle character alignment mode enables aligned transfers with automatic realignment or unaligned data transfers (if in 10 bit mode).
- Received data may be clocked to the recovered clock or to the reference clock frequencies.
- Compatibility mode enables non-intrusive operation with packet data streams.
• Link Interface Features
- Drives 50 or 75 media (100 or 150 differential) for lengths of up to 1.5meters board/backplane, or 10 meters of coax.
- Link inputs have on-chip receiver termination and are "hot swap" compatible.
- Tolerates a frequency offset between the transmitter and receiver in excess of +250ppm.
MC92602
PDF/DataSheet Download
- Datasheet: MC92602
- File Size: 917759 KB
- Manufacturer: Motorola
- Click here to Download
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