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Part Number: MCF5271
Description: The MCF5271 family is a highly integrated Table of Contents implementation of the ColdFire® family...
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General Description
MCF5271 General Description
The MCF5271 family is a highly integrated Table of Contents implementation of the ColdFire® family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent features and functions of the MCF5271 family. The MCF5271 family includes the MCF5271 and MCF5270 microprocessors. The differences between these parts are summarized below in Table 1. This document is written from the perspective of the MCF5271 and unless otherwise noted, the information applies also to the MCF5270.
The MCF5271 family combines low cost with high integration on the popular version 2 ColdFire core with over 96 (Dhrystone 2.1) MIPS at 100MHz. Positioned for applications requiring a cost-sensitive 32-bit solution, the MCF5271 family features a 10/100 Ethernet MAC and optional hardware encryption to ensure the application can be connected and protected. In addition, the MCF5271 family features an enhanced Multiply Accumulate Unit (eMAC), large on-chip memory (64 Kbytes SRAM, 8 Kbytes configurable cache), and a 32-bit SDR SDRAM memory controller.
MCF5271 Maximum Ratings
| Rating | Symbol | Value | Unit |
| Core Supply Voltage | VDD | 0.5 to +2.0 | V |
| Pad Supply Voltage | OVDD | 0.3 to +4.0 | V |
| Clock Synthesizer Supply Voltage | VDDPLL | 0.3 to +4.0 | V |
| Digital Input Voltage 3 | VIN | 0.3 to +4.0 | V |
| Instantaneous Maximum Current Single pin limit (applies to all pins) 3,4,5 |
ID | 25 | mA |
| Operating Temperature Range (Packaged) | TA (TL - TH |
40 to 85 | °C |
| Storage Temperature Range | Tstg | 65 to 150 | °C |
MCF5271 Features
• Version 2 ColdFire variable-length RISC processor core
- Static operation
- 32-bit address and data path on-chip
- Processor core runs at twice the bus frequency
- Sixteen general-purpose 32-bit data and address registers
- Implements the ColdFire Instruction Set Architecture, ISA_A, with extensions to support the
user stack pointer register, and 4 new instructions for improved bit processing
- Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit
signal processing algorithms
- Illegal instruction decode that allows for 68K emulation support
• System debug support
- Real time trace for determining dynamic execution path
- Background debug mode (BDM) for in-circuit debugging
- Real time debug support, with two user-visible hardware breakpoint registers (PC and address
with optional data) that can be configured into a 1- or 2-level trigger
• On-chip memories
- 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
- 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus
masters (e.g., DMA, FEC)
• Fast Ethernet Controller (FEC)
- 10 BaseT capability, half duplex or full duplex
- 100 BaseT capability, half duplex or full duplex
- On-chip transmit and receive FIFOs
- Built-in dedicated DMA controller
- Memory-based flexible descriptor rings
- Media independent interface (MII) to external transceiver (PHY)
• Three Universal Asynchronous Receiver Transmitters (UARTs)
- 16-bit divider for clock generation
- Interrupt control logic
- Maskable interrupts
- DMA support
- Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
- Up to 2 stop bits in 1/16 increments
- Error-detection capabilities
- Modem support includes request-to-send (URTS) and clear-to-send (UCTS) lines for two UARTs
- Transmit and receive FIFO buffers
• I2C Module
- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
- Fully compatible with industry-standard I2C bus
- Master or slave modes support multiple masters
- Automatic interrupt generation with programmable level
• Queued Serial Peripheral Interface (QSPI)
- Full-duplex, three-wire synchronous transfers
- Up to four chip selects available
- Master mode operation only
- Programmable master bit rates
- Up to 16 pre-programmed transfers
• Four 32-bit DMA Timers
- 20-ns resolution at 50 MHz
- Programmable sources for clock input, including an external clock option
- Programmable prescaler
- Input-capture capability with programmable trigger edge on input pin
- Output-compare with programmable mode for the output pin
- Free run and restart modes
- Maskable interrupts on input capture or reference-compare
- DMA trigger capability on input capture or reference-compare
• Four Periodic Interrupt Timers (PITs)
- 16-bit counter
- Selectable as free running or count down
• Software Watchdog Timer
- 16-bit counter
- Low power mode support
• Frequency Modulated Phase Locked Loop (PLL)
- Crystal or external oscillator reference
- 8 to 25 MHz reference frequency for normal PLL mode
- 24 to 50 MHz oscillator reference frequency for 1:1 mode
- Separate clock output pin
- Interrupt Controllers (x2)
Support for up to 41 interrupt sources organized as follows: 34 fully-programmable
interrupt sources and 7 fixed-level external interrupt sources
- Unique vector number for each interrupt source
- Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
- Support for hardware and software interrupt acknowledge (IACK) cycles
- Combinatorial path to provide wake-up from low power modes
• DMA Controller
- Four fully programmable channels
- Dual-address and single-address transfer support with 8-, 16- and 32-bit data capability along
with support for 16-byte (4 x 32-bit) burst transfers
- Source/destination address pointers that can increment or remain constant
- 24-bit byte transfer counter per channel
- Auto-alignment transfers supported for efficient block movement
- Bursting and cycle steal support
- Software-programmable connections between the 12 DMA requesters in the UARTs (3),
32-bit timers (4), plus external logic (4), and the four DMA channels (4)
• External Bus Interface
- Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.)
- SDRAM controller supports 8-, 16-, and 32-bit wide memory devices
- Support for n-1-1-1 burst fetches from page mode Flash
- Glueless interface to SRAM devices with or without byte strobe inputs
- Programmable wait state generator
- 32-bit bidirectional data bus
- 24-bit address bus
- Up to eight chip selects available
- Byte/write enables (byte strobes)
- Ability to boot from external memories that are 8, 16, or 32 bits wide
• Chip Configuration Module (CCM)
- System configuration during reset
- Selects one of four clock modes
- Sets boot device and its data port width
- Configures output pad drive strength
- Unique part identification number and part revision number
- Reset
Separate reset in and reset out signals
Six sources of reset: Power-on reset (POR), External, Software, Watchdog, PLL loss of
clock, PLL loss of lock
Status flag indication of source of last reset
• General Purpose I/O interface
- Up to 61 bits of general purpose I/O
- Bit manipulation supported via set/clear functions
- Unused peripheral pins may be used as extra GPIO
• JTAG support for system level board testing
- Static operation
- 32-bit address and data path on-chip
- Processor core runs at twice the bus frequency
- Sixteen general-purpose 32-bit data and address registers
- Implements the ColdFire Instruction Set Architecture, ISA_A, with extensions to support the
user stack pointer register, and 4 new instructions for improved bit processing
- Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit
signal processing algorithms
- Illegal instruction decode that allows for 68K emulation support
• System debug support
- Real time trace for determining dynamic execution path
- Background debug mode (BDM) for in-circuit debugging
- Real time debug support, with two user-visible hardware breakpoint registers (PC and address
with optional data) that can be configured into a 1- or 2-level trigger
• On-chip memories
- 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
- 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus
masters (e.g., DMA, FEC)
• Fast Ethernet Controller (FEC)
- 10 BaseT capability, half duplex or full duplex
- 100 BaseT capability, half duplex or full duplex
- On-chip transmit and receive FIFOs
- Built-in dedicated DMA controller
- Memory-based flexible descriptor rings
- Media independent interface (MII) to external transceiver (PHY)
• Three Universal Asynchronous Receiver Transmitters (UARTs)
- 16-bit divider for clock generation
- Interrupt control logic
- Maskable interrupts
- DMA support
- Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
- Up to 2 stop bits in 1/16 increments
- Error-detection capabilities
- Modem support includes request-to-send (URTS) and clear-to-send (UCTS) lines for two UARTs
- Transmit and receive FIFO buffers
• I2C Module
- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
- Fully compatible with industry-standard I2C bus
- Master or slave modes support multiple masters
- Automatic interrupt generation with programmable level
• Queued Serial Peripheral Interface (QSPI)
- Full-duplex, three-wire synchronous transfers
- Up to four chip selects available
- Master mode operation only
- Programmable master bit rates
- Up to 16 pre-programmed transfers
• Four 32-bit DMA Timers
- 20-ns resolution at 50 MHz
- Programmable sources for clock input, including an external clock option
- Programmable prescaler
- Input-capture capability with programmable trigger edge on input pin
- Output-compare with programmable mode for the output pin
- Free run and restart modes
- Maskable interrupts on input capture or reference-compare
- DMA trigger capability on input capture or reference-compare
• Four Periodic Interrupt Timers (PITs)
- 16-bit counter
- Selectable as free running or count down
• Software Watchdog Timer
- 16-bit counter
- Low power mode support
• Frequency Modulated Phase Locked Loop (PLL)
- Crystal or external oscillator reference
- 8 to 25 MHz reference frequency for normal PLL mode
- 24 to 50 MHz oscillator reference frequency for 1:1 mode
- Separate clock output pin
- Interrupt Controllers (x2)
Support for up to 41 interrupt sources organized as follows: 34 fully-programmable
interrupt sources and 7 fixed-level external interrupt sources
- Unique vector number for each interrupt source
- Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
- Support for hardware and software interrupt acknowledge (IACK) cycles
- Combinatorial path to provide wake-up from low power modes
• DMA Controller
- Four fully programmable channels
- Dual-address and single-address transfer support with 8-, 16- and 32-bit data capability along
with support for 16-byte (4 x 32-bit) burst transfers
- Source/destination address pointers that can increment or remain constant
- 24-bit byte transfer counter per channel
- Auto-alignment transfers supported for efficient block movement
- Bursting and cycle steal support
- Software-programmable connections between the 12 DMA requesters in the UARTs (3),
32-bit timers (4), plus external logic (4), and the four DMA channels (4)
• External Bus Interface
- Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.)
- SDRAM controller supports 8-, 16-, and 32-bit wide memory devices
- Support for n-1-1-1 burst fetches from page mode Flash
- Glueless interface to SRAM devices with or without byte strobe inputs
- Programmable wait state generator
- 32-bit bidirectional data bus
- 24-bit address bus
- Up to eight chip selects available
- Byte/write enables (byte strobes)
- Ability to boot from external memories that are 8, 16, or 32 bits wide
• Chip Configuration Module (CCM)
- System configuration during reset
- Selects one of four clock modes
- Sets boot device and its data port width
- Configures output pad drive strength
- Unique part identification number and part revision number
- Reset
Separate reset in and reset out signals
Six sources of reset: Power-on reset (POR), External, Software, Watchdog, PLL loss of
clock, PLL loss of lock
Status flag indication of source of last reset
• General Purpose I/O interface
- Up to 61 bits of general purpose I/O
- Bit manipulation supported via set/clear functions
- Unused peripheral pins may be used as extra GPIO
• JTAG support for system level board testing
MCF5202
PDF/DataSheet Download
- Datasheet: MCF5202
- File Size: 909005 KB
- Manufacturer: Motorola
- Click here to Download
- ·MCF5204
- Motorola
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- MOTOROLA [Motorola, Inc]
- MCF5206 Integrated Microprocessor
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- 1249956 KB
- ·MCF5232
- FREESCALE [Freescale Semiconductor, Inc]
- Integrated Microprocessor Hardware Specification
- 1497838 KB
- ·MCF5233
- FREESCALE [Freescale Semiconductor, Inc]
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- 1497838 KB
- ·MCF5234
- FREESCALE [Freescale Semiconductor, Inc]
- Integrated Microprocessor Hardware Specification
- 1497838 KB
- ·MCF5235
- FREESCALE [Freescale Semiconductor, Inc]
- Integrated Microprocessor Hardware Specification
- 1497838 KB
- ·MCF523X
- FREESCALE [Freescale Semiconductor, Inc]
- Integrated Microprocessor Hardware Specification
- 1497838 KB
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