MCM62486B

The MCM62486B is a 294,912 bit synchronous static random access memory designed to provide a burstable, highperformance, secondary cache for the i486 and PentiumE microprocessors. It is organized as 32,768 words of 9 bits, fabricated with Motorola's highperformance silicongate CMOS technology. The device integrates input registers, a 2bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

Addresses (A0 A14), data inputs (D0 D8), and all control signals except output enable (G) are clock (K) controlled through positiveedgetriggered noninverting registers.

Bursts can be initiated with either address status processor (ADSP) or address status cache controller (ADSC) input pins. Subsequent burst addresses can be generated internally by the MCM62486B (burst sequence imitates that of the i486 and Pentium) and controlled by the burst address advance (ADV) input pin.

The following pages provide more detailed information on burst controls.

Write cycles are internally selftimed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex offchip write pulse generation and provides increased flexibility for incoming signals.

The MCM62486B will be available in a 44pin plastic leaded chip carrier (PLCC). Multiple power and ground pins have been utilized to minimize effects induced by output noise. Separate power and ground pins have been employed for DQ0 DQ8 to allow usercontrolled output levels of 5 volts or 3.3 volts.