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Part Number: MCM63P531
Description: The MCM63P531 is a 1M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cach...
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MCM63P531
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DataSheet
General Description
MCM63P531 General Description
The MCM63P531 is a 1M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC(TM), and Pentium(TM) microprocessors. It is organized as 32K words of 32 bits each, fabricated using high performance silicon gate CMOS technology. This device ntegrates input registers, an output register, a 2bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
MCM63P531 Maximum Ratings
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 2 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 2 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
MCM63P531 Features
* MCM63P5314.5 = 4.5 ns access / 10 ns cycle
MCM63P5317 = 7 ns access / 13.3 ns cycle
MCM63P5318 = 8 ns access / 15 ns cycle
MCM63P5319 = 9 ns access / 16.6 ns cycle
* Single 3.3 V + 10%, 5% Power Supply
* ADSP, ADSC, and ADV Burst Control Pins
* Selectable Burst Sequencing Order (Linear/Interleaved)
* Internally SelfTimed Write Cycle
* Byte Write and Global Write Control
* Sleep Mode (ZZ)
* Intel PBSRAM 2.0 Compliant
* SingleCycle Deselect Timing
* 100 Pin TQFP Package
MCM63P5317 = 7 ns access / 13.3 ns cycle
MCM63P5318 = 8 ns access / 15 ns cycle
MCM63P5319 = 9 ns access / 16.6 ns cycle
* Single 3.3 V + 10%, 5% Power Supply
* ADSP, ADSC, and ADV Burst Control Pins
* Selectable Burst Sequencing Order (Linear/Interleaved)
* Internally SelfTimed Write Cycle
* Byte Write and Global Write Control
* Sleep Mode (ZZ)
* Intel PBSRAM 2.0 Compliant
* SingleCycle Deselect Timing
* 100 Pin TQFP Package
MCM63P531 Connection Diagram
MCM63P531
PDF/DataSheet Download
- Datasheet: MCM63P531
- File Size: 342514 KB
- Manufacturer: MOTOROLA [Motorola, Inc]
- Click here to Download
- ·MCM101524
- MOTOROLA [Motorola, Inc]
- 1M x 4 Bit Fast Static Random Access Memory with ECL I/O
- 465614 KB
- ·MCM101524B12
- MOTOROLA [Motorola, Inc]
- 1M x 4 Bit Fast Static Random Access Memory with ECL I/O
- 465614 KB
- ·MCM101524B15
- MOTOROLA [Motorola, Inc]
- 1M x 4 Bit Fast Static Random Access Memory with ECL I/O
- 465614 KB
- ·MCM101525
- MOTOROLA [Motorola, Inc]
- 2M x 2 Bit Fast Static Random Access Memory with ECL I/O
- 465805 KB
- ·MCM101525B12
- MOTOROLA [Motorola, Inc]
- 2M x 2 Bit Fast Static Random Access Memory with ECL I/O
- 465805 KB
- ·MCM101525B15
- MOTOROLA [Motorola, Inc]
- 2M x 2 Bit Fast Static Random Access Memory with ECL I/O
- 465805 KB
- ·MCM14537
- MOTOROLA [Motorola, Inc]
- CMOS LSI
- 394028 KB
- ·MCM14537CAL
- MOTOROLA [Motorola, Inc]
- CMOS LSI
- 394028 KB
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