MCM67A618B

The MCM67A618B is a 1,179,648 bit latched address static random access memory organized as 65,536 words of 18 bits. The device integrates a 64K x 18 SRAM core with advanced peripheral circuitry consisting of address and data in- put latches, active low chip enable, separate upper and lower byte write strobes, and a fast output enable. This device has increased output drive capability sup-ported by multiple power pins.

Address, data in, and chip enable latches are provided. When latch enables (AL for address and chip enables and DL for data in) are high, the address, data in, and chip enable latches are in the transparent state. If latch enables are tied high the device can be used as an asynchronous SRAM. When latch enables are low the address, data in, and chip enable latches are in the latched state. This input latch simplifies read and write cycles by guaranteeing address and datain hold time in a simple fashion.

Dual write enables (LW</a> and UW</a> ) are provided to allow individually writeable bytes. LW</a>  controls DQ0 DQ8 (the lower bits) while UW</a> controls DQ9 DQ17 (the upper bits).

Six pair of power and ground pins have been utilized and placed on the package for maximum performance.

The MCM67A618B will be available in a 52pin plastic leaded chip carrier (PLCC).

This device is ideally suited for systems that require wide data bus widths, cache memory, and tag RAMs.