MCM69P536C

The MCM69P536C BurstRAM is a high speed synchronous SRAM that is intended for use primarily in secondary or level two (L2) cache memory applications. L2 caches are found in a variety of classes of computers - from the desktop personal computer to the highend servers and transaction processing machines. For simplicity, the majority of L2 caches today are direct mapped and are single bank implementations. These caches tend to be designed for bus speeds in the range of 33 to 66 MHz. At these bus rates, nonpipelined (flowthrough) BurstRAMs can be used since their access times meet the speed requirements for a minimum latency, zerowait state L2 cache interface. Latency is a measure (time) of "dead" time the memory system exhibits as a result of a memory request.
For those applications that demand bus operation at greater than 66 MHz or multibank L2 caches at 66 MHz, the pipelined (register/register) version of the 32Kx36 BurstRAM (MCM69P536C) allows the designer to maintain zerowait state operation. Multiple banks of BurstRAMs create additional bus loading and can cause the system to otherwise miss its timing requirements. The access time (clocktovaliddata) of a pipelined BurstRAM is inherently faster than a nonpipelined device by a few nanoseconds. This does not come without cost. The cost is latency - "dead" time.
Since most L2 caches are tied to the processor bus and bus speeds continue to increase over time, pipelined (R/R) BurstRAMs are the best choice in achieving zerowait state L2 cache performance. At bus speeds ranging from 66 MHz to 100 MHz, pipelined BurstRAMs are able to provide fast clock to valid data times required of these high speed buses.