MCM69P536CTQ7R

The MCM69P536CTQ7R is one member of the MCM69P536C series.The MCM69P536C is a 1Mbit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family,PowerPC(TM), 486, i960(TM), and Pentium(TM) microprocessors. It is organized as 32K words of 36 bits each. This device integrates input registers, an output register,a 2bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

Features of the MCM69P536CTQ7R are:(1)single 3.3 V +10%, -5% power supply; (2)ADSP, ADSC, and ADV burst control pins; (3)selectable burst sequencing order (linear/interleaved); (4)internally selftimed write cycle; (5)byte write and global write control; (6)5 V tolerant on all pins (inputs and I/Os); (7)100pin TQFP package.Write cycles are internally selftimed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incoming signals.

The absolute maximum ratings of the MCM69P536CTQ7R can be summarized as:(1)power supply voltage:0.5 to + 4.6V;(2)voltage relative to Vss for any pin except VDD:0.5 to 6.0 V;(3)storage temperature:-55 to 125;(4)temperature under bias:-10 to 85;(5)package power dissipation:1.6W.This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this highimpedance circuit.The MCM69P536C BurstRAM is a high speed synchronous SRAM that is intended for use primarily in secondary or level two (L2) cache memory applications. L2 caches are found in a variety of classes of computers--- from the desk-top personal computer to the highend servers and transaction processing machines. For simplicity, the majority of L2 caches today are direct mapped and are single bank implementations.