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Part Number: MCM69R618
Description: The MCM69R536/618 is a 1 megabit synchronous late write fast static RAM designed to provide high perfo...
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MCM69R618
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General Description
MCM69R618 General Description
The MCM69R536/618 is a 1 megabit synchronous late write fast static RAM designed to provide high performance in secondary cache, ATM switch, Telecom, and other high speed memory applications. The MCM69R618 organized as 64K words by 18 bits, and the MCM69R536 organized as 32K words by 36 bits wide are fabricated in Motorola's high performance silicon gate BiCMOS technology.
The differential CK clock inputs control the timing of read/write operations of the RAM. At the rising edge of the CK clock all addresses, write enables, and synchronous selects are registered. An internal buffer and special logic enable the memory to accept write data on the rising edge of the CK clock a cycle after address and control signals. Read data is driven on the rising edge of the CK clock also.
The RAM uses HSTL inputs and outputs. The adjustable input trip point (Vref) and output voltage (VDDQ) gives the system designer greater flexibility in optimizing system performance. The synchronous write and byte enables allow writing to individual bytes or the entire word.
The impedance of the output buffers is programmable allowing the outputs to match the impedance of the circuit traces which reduces signal reflections.
MCM69R618 Maximum Ratings
| Rating | Symbol | Value | Unit |
| Core Supply Voltage | VDD | 0.5 to + 4.6 | V |
| Output Supply Voltage | VDDQ | 0.5 to VDD + 0.5 | V |
| Voltage On Any Pin | Vin | 0.5 to VDD + 0.5 | V |
| Input Current (per I/O) | Iin | ± 50 | mA |
| Output Current (per I/O) | Iout | ± 70 | mA |
| Power Dissipation (See Note 2) | PD | - | W |
| Operating Temperature | TA | 0 to + 70 | °C |
| Temperature Under Bias | Tbias | 10 to + 85 | °C |
| Storage Temperature | Tstg | 55 to + 125 | °C |
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
2. Power dissipation capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.
MCM69R618 Features
• Byte Write Control
• Single 3.3 V + 10%, 5% Operation
• HSTL I/O (JEDEC Standard JESD86 Class 1 Compatible)
• HSTL User Selectable Input TripPoint
• HSTL Compatible Programmable Impedance Output Drivers
• Register to Register Synchronous Operation
• Asynchronous Output Enable
• Boundary Scan (JTAG) IEEE 1149.1 Compatible
• Differential Clock Inputs
• Optional x18 or x36 organization
• MCM69R536/6185 = 5 ns
MCM69R536/6186 = 6 ns
MCM69R536/6187 = 7 ns
MCM69R536/6188 = 8 ns
• 119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array (PBGA) Package
• Single 3.3 V + 10%, 5% Operation
• HSTL I/O (JEDEC Standard JESD86 Class 1 Compatible)
• HSTL User Selectable Input TripPoint
• HSTL Compatible Programmable Impedance Output Drivers
• Register to Register Synchronous Operation
• Asynchronous Output Enable
• Boundary Scan (JTAG) IEEE 1149.1 Compatible
• Differential Clock Inputs
• Optional x18 or x36 organization
• MCM69R536/6185 = 5 ns
MCM69R536/6186 = 6 ns
MCM69R536/6187 = 7 ns
MCM69R536/6188 = 8 ns
• 119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array (PBGA) Package
MCM69R618
PDF/DataSheet Download
- Datasheet: MCM69R618
- File Size: 144762 KB
- Manufacturer: Motorola
- Click here to Download
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The MCM69R536/618 is a 1 megabit synchronous late write fast static RAM designed to provide high performance in secondary cache, ATM switch, Telecom, and other high speed memory applications. The MCM69R618 organized as 64K words by 18 bits, and the MCM69R536...
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