MG2194

The MG2 series is a 0.5 micron, array based, CMOS product family. Several arrays up to 700k cells cover all system integration needs. The MG2 is manufactured using SCMOS3/2, a 0.5 micron drawn, 3 metal layers CMOS process.
 
The MG2 series base cell architecture provides high routability of logic with extremely dense compiled memories : RAM, DPRAM and FIFO. ROM MG2 series can be generated using synthesis tools. For instance, the largest array is capable of integrating 128K bits of DPRAM with 128K bits of ROM and over 300,000 random gates.

Accurate control of clock distribution can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques of MG2 series are applied in the array and in the periphery : Three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level.

The MG2 is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Cadence, Mentor, Synopsys and VHDL are the reference front end tools. Floor planning of MG2 series associated with timing driven layout provides a short back end cycle.

The MG2 family continues the TEMIC offering in array based commercial, industrial and military circuits.