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MFG:ATMEL D/C:08+
Part Number: MG2RTP
MFG: ATMEL
D/C: 08+
Description: The MG2RTP series is a 0.5 micron, array based, CMOS product family. Several arrays up to 490k cells c...
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MG2RTP
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General Description
MG2RTP General Description
The MG2RTP series is a 0.5 micron, array based, CMOS product family. Several arrays up to 490k cells cover all system integration needs. The MG2RTP is manufactured using a 0.5 micron drawn, 3 metal layers CMOS process.
The MG2RTP series base cell architecture provides high routability of logic with extremely dense compiled memories: RAM and DPRAM. ROM can be generated using synthesis tools.
Accurate control of clock distribution can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques are applied in the array and in the periphery: three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level.
MG2RTP Maximum Ratings
Ambient temperature under bias (TA)
Military -55 to +125°C
Junction temperature TJ < TA + 20°C
Storage temperature -65 to +150°C
TTL/CMOS:
Supply voltage VDD-0.5 V to +6 V
I/O voltage -0.5 V to VDD + 0.5 V
Note: Stresses above those listed may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended period may affect device reliability.
MG2RTP Features
• Full Range of Matrices up to 490k Cells
• 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates
• RAM and DPRAM Compilers
• Library Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATG)
• 3 and 5 volts operation: single or dual supply mode
• High Speed Performances:
640 ps max. NAND2 propagation Delay @5V and FO = 1/4 FO max.
min. 440 MHz Toggle Frequency @4.5V, 230 MHz @2.7V
• Programmable PLL available on request
• High System Frequency Skew Control:
200 MHz max. PLL for Clock Generation @4.5V.
Clock Tree Synthesis Software
• Low Power Consumption:
2 µW/Gate/MHz @5V
0.6 µW/Gate/MHz @3V
• Matrices With a max of 484full programmable Pads
• Standard 3, 6, 12 and 24mA I/Os
• Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator
• CMOS/TTL/PCI Interface
• ESD (2 kV) And Latch-up Protected I/O
• Wide Selection of MQFPs and CLGA packages up to 564 pins
• High Noise & EMC Immunity:
I/O with Slew Rate Control
Internal Decoupling
Signal Filtering between Periphery & Core
Application Dependent Supply Routing & Several Independant Supply Sources
• Delivery in Die Form with 110µm pad pitch
• Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management
• Cadence, Mentor, Vital & Synopsys Reference Platforms
• EDIF & VHDL Reference Formats
• Available In Military and Space Quality Grades (SCC, MIL-PRF-38535)
• Latch up immune
• Total dose better than 300 Krads (TM1019.5)
• QML Q & V with SMD 5962-00B03
• 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates
• RAM and DPRAM Compilers
• Library Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATG)
• 3 and 5 volts operation: single or dual supply mode
• High Speed Performances:
640 ps max. NAND2 propagation Delay @5V and FO = 1/4 FO max.
min. 440 MHz Toggle Frequency @4.5V, 230 MHz @2.7V
• Programmable PLL available on request
• High System Frequency Skew Control:
200 MHz max. PLL for Clock Generation @4.5V.
Clock Tree Synthesis Software
• Low Power Consumption:
2 µW/Gate/MHz @5V
0.6 µW/Gate/MHz @3V
• Matrices With a max of 484full programmable Pads
• Standard 3, 6, 12 and 24mA I/Os
• Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator
• CMOS/TTL/PCI Interface
• ESD (2 kV) And Latch-up Protected I/O
• Wide Selection of MQFPs and CLGA packages up to 564 pins
• High Noise & EMC Immunity:
I/O with Slew Rate Control
Internal Decoupling
Signal Filtering between Periphery & Core
Application Dependent Supply Routing & Several Independant Supply Sources
• Delivery in Die Form with 110µm pad pitch
• Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management
• Cadence, Mentor, Vital & Synopsys Reference Platforms
• EDIF & VHDL Reference Formats
• Available In Military and Space Quality Grades (SCC, MIL-PRF-38535)
• Latch up immune
• Total dose better than 300 Krads (TM1019.5)
• QML Q & V with SMD 5962-00B03
MG2RTP
PDF/DataSheet Download
- Datasheet: MG2RTP
- File Size: 151849 KB
- Manufacturer: Atmel
- Click here to Download
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