MG2RT

The MG2RT series is a 0.5 micron, array based, CMOS product family. Several arrays up to 700K cells cover all system integration needs. The MG2RT is manufactured using a 0.5 micron drawn, 3 metal layer CMOS process.

The base cell architecture of the MG2RT series provides high routability of logic with extremely dense compiled memories: RAM and DPRAM. ROM can be generated using synthesis tools. For instance, the largest array is capable of integrating 128K bits and DPRAM with 128K bits of ROM and over 300,000 random gates.

Accurate control of clock distribution can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques are applied in the array and in the periphery: Three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level.

The MG2RT is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Cadence, Mentor, Synopsys and- VHDL are the reference front-end tools. Floor planning associated with timing-driven layout provides a short back-end cycle.